EXPORT void CORE_reg_write(int r, uint32_t val) {
assert(r >= 0 && r < 16 && "CORE_reg_write");
if (r == SP_REG) {
SW(physical_sp_p, val & 0xfffffffc);
} else if (r == LR_REG) {
SW(&physical_lr, val);
} else if (r == PC_REG) {
DBG2("Writing %08x to PC\n", val & 0xfffffffe);
#ifdef NO_PIPELINE
pipeline_flush_exception_handler(val & 0xfffffffe);
#else
if (state_is_debugging()) {
DBG1("PC write + debugging --> flush\n");
state_pipeline_flush(val & 0xfffffffe);
} else {
// Only flush if the new PC differs from predicted in pipeline:
if (((SR(&if_id_PC) & 0xfffffffe) - 4) == (val & 0xfffffffe)) {
DBG2("Predicted PC correctly (%08x)\n", val);
} else {
state_pipeline_flush(val & 0xfffffffe);
DBG2("Predicted PC incorrectly\n");
DBG2("Pred: %08x, val: %08x\n", SR(&if_id_PC), val);
}
}
#endif
}
else {
SW(&(physical_reg[r]), val);
}
}
EXPORT void CORE_reg_write(int r, uint32_t val) {
assert(r >= 0 && r < 16 && "CORE_reg_write");
if (r == SP_REG) {
SW(&SP, val & 0xfffffffc);
} else if (r == LR_REG) {
SW(&LR, val);
} else if (r == PC_REG) {
#ifdef NO_PIPELINE
/*
if (*state_flags_cur & STATE_DEBUGGING) {
SW(&pre_if_PC, val & 0xfffffffe);
SW(&if_id_PC, val & 0xfffffffe);
SW(&id_ex_PC, val & 0xfffffffe);
} else {
*/
SW(&pre_if_PC, val & 0xfffffffe);
//}
#else
if (state_is_debugging()) {
state_pipeline_flush(val & 0xfffffffe);
} else {
// Only flush if the new PC differs from predicted in pipeline:
if (((SR(&if_id_PC) & 0xfffffffe) - 4) == (val & 0xfffffffe)) {
DBG2("Predicted PC correctly (%08x)\n", val);
} else {
state_pipeline_flush(val & 0xfffffffe);
DBG2("Predicted PC incorrectly\n");
DBG2("Pred: %08x, val: %08x\n", SR(&if_id_PC), val);
}
}
#endif
}
else {
SW(&(reg[r]), val);
}
}