static int stm32_tim_setcompare(FAR struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare)
{
ASSERT(dev);
switch (channel)
{
case 1:
stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare);
break;
case 2:
stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare);
break;
case 3:
stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare);
break;
case 4:
stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare);
break;
default:
return ERROR;
}
return OK;
}
static int stm32_cap_setclock(FAR struct stm32_cap_dev_s *dev, stm32_cap_clk_t clk,
uint32_t prescaler,uint32_t max)
{
const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev;
uint16_t regval = 0;
if (prescaler == 0)
{
/* Disable Timer */
stm32_modifyreg16(priv, STM32_BTIM_CR1_OFFSET, ATIM_CR1_CEN, 0);
return 0;
}
/* We need to decrement value for '1', but only, if we are allowed to
* not to cause underflow. Check for overflow.
*/
if (prescaler > 0)
{
prescaler--;
}
if (prescaler > 0xffff)
{
prescaler = 0xffff;
}
switch(clk)
{
case STM32_CAP_CLK_INT:
regval = GTIM_SMCR_DISAB;
break;
case STM32_CAP_CLK_EXT:
regval = GTIM_SMCR_EXTCLK1;
break;
/* TODO: Add other case */
default:
return ERROR;
}
stm32_modifyreg16(priv, STM32_BTIM_EGR_OFFSET, GTIM_SMCR_SMS_MASK, regval);
/* Set Maximum */
stm32_putreg32(priv, STM32_BTIM_ARR_OFFSET, max);
/* Set prescaler */
stm32_putreg16(priv, STM32_BTIM_PSC_OFFSET, prescaler);
/* Reset counter timer */
stm32_modifyreg16(priv, STM32_BTIM_EGR_OFFSET, 0, BTIM_EGR_UG);
/* Enable timer */
stm32_modifyreg16(priv, STM32_BTIM_CR1_OFFSET, 0, BTIM_CR1_CEN);
#ifdef USE_ADVENCED_TIM
/* Advanced registers require Main Output Enable */
if (priv->base == STM32_TIM1_BASE || priv->base == STM32_TIM8_BASE)
{
stm32_modifyreg16(priv, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE);
}
#endif
return prescaler;
}
static void stm32_tim_setperiod(FAR struct stm32_tim_dev_s *dev, uint32_t period)
{
ASSERT(dev);
stm32_putreg32(dev, STM32_BTIM_ARR_OFFSET, period);
}
