/*
* Configure GPIOs
*/
static int pwr_setup_gpio(void)
{
struct stm32f2_gpio_dsc pwr_en_gpio[] = {
{ STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_10 }, /* PWR_EN */
{ STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_0 }, /* LCD_DIM */
};
int i, rv;
for (i = 0; i < ARRAY_SIZE(pwr_en_gpio); i++) {
rv = stm32f2_gpio_config(&pwr_en_gpio[i],
STM32F2_GPIO_ROLE_GPOUT);
if (rv)
goto out;
rv = stm32f2_gpout_set(&pwr_en_gpio[i], 1);
if (rv)
goto out;
}
out:
return rv;
}
/*
* Setup external RAM.
*/
int dram_init(void)
{
int rv = 0;
#if 0
static struct stm32f2_gpio_dsc ctrl_gpio = {STM32F2_GPIO_PORT_I,
STM32F2_GPIO_PIN_9};
rv = fsmc_nor_psram_init(CONFIG_SYS_RAM_CS,
CONFIG_SYS_FSMC_PSRAM_BCR,
CONFIG_SYS_FSMC_PSRAM_BTR,
#ifdef CONFIG_SYS_FSMC_PSRAM_BWTR
CONFIG_SYS_FSMC_PSRAM_BWTR
#else
(u32)-1
#endif
);
if (rv != 0)
goto out;
rv = stm32f2_gpio_config(&ctrl_gpio, STM32F2_GPIO_ROLE_GPOUT);
if (rv != 0)
goto out;
# if defined(CONFIG_SYS_RAM_BURST)
/*
* FIXME: all this hardcoded stuff.
*/
/* Step.2 */
stm32f2_gpout_set(&ctrl_gpio, 1);
/* Step.3 */
*(volatile u16 *)(CONFIG_SYS_RAM_BASE + 0x0010223E) = 0;
/* Step.4-5 */
stm32f2_gpout_set(&ctrl_gpio, 0);
/* Step.6 */
fsmc_nor_psram_init(CONFIG_SYS_RAM_CS, 0x00083115,
0x0010FFFF, -1);
/* Step.7 */
rv = *(volatile u16 *)(CONFIG_SYS_RAM_BASE + 0x000000);
/* Step.8 */
fsmc_nor_psram_init(CONFIG_SYS_RAM_CS, 0x00005059,
0x10000702, 0x10000602);
/* Step.9 */
stm32f2_gpout_set(&ctrl_gpio, 1);
/* Step.10 */
*(volatile u16 *)(CONFIG_SYS_RAM_BASE + 0x0110223E) = 0;
/* Step.11 */
stm32f2_gpout_set(&ctrl_gpio, 0);
/* Step.12 */
fsmc_nor_psram_init(CONFIG_SYS_RAM_CS, 0x00083115,
0x0010FFFF, -1);
/* Step.13 */
rv = *(volatile u16 *)(CONFIG_SYS_RAM_BASE + 0x01000000);
# else
/*
* Switch PSRAM in the Asyncronous Read/Write Mode
*/
stm32f2_gpout_set(&ctrl_gpio, 0);
# endif /* CONFIG_SYS_RAM_BURST */
#endif
/*
* Fill in global info with description of SRAM configuration
*/
gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE;
rv = 0;
out:
return rv;
}
