static bool stm32f4_cmd_option(target *t, int argc, char *argv[])
{
uint32_t start, val;
int len;
if (t->idcode == 0x449) {
start = 0x1FFF0000;
len = 0x20;
}
else {
start = 0x1FFFC000;
len = 0x10;
}
if ((argc == 2) && !strcmp(argv[1], "erase")) {
stm32f4_option_write(t, 0x0fffaaed);
}
else if ((argc == 3) && !strcmp(argv[1], "write")) {
val = strtoul(argv[2], NULL, 0);
stm32f4_option_write(t, val);
} else {
gdb_out("usage: monitor option erase\n");
gdb_out("usage: monitor option write <value>\n");
}
for (int i = 0; i < len; i += 8) {
uint32_t addr = start + i;
val = target_mem_read32(t, addr);
gdb_outf("0x%08X: 0x%04X\n", addr, val & 0xFFFF);
}
return true;
}
static bool stm32f4_option_write_default(target *t)
{
uint32_t val[3];
switch (t->idcode) {
case ID_STM32F42X:
case ID_STM32F46X:
val[0] = 0x0FFFAAED;
val[1] = 0x0FFF0000;
return stm32f4_option_write(t, val, 2);
case ID_STM32F72X:
val[0] = 0xC0FFAAFD;
val[1] = 0x00400080;
val[2] = 0;
return stm32f4_option_write(t, val, 3);
case ID_STM32F74X:
val[0] = 0xC0FFAAFD;
val[1] = 0x00400080;
return stm32f4_option_write(t, val, 2);
case ID_STM32F76X:
val[0] = 0xFFFFAAFD;
val[1] = 0x00400080;
return stm32f4_option_write(t, val, 2);
case ID_STM32F413:
val[0] = 0x7FFFAAFD;
return stm32f4_option_write(t, val, 1);
default:
val[0] = 0x0FFFAAED;
return stm32f4_option_write(t, val, 1);
}
}
static bool stm32f4_cmd_option(target *t, int argc, char *argv[])
{
uint32_t start = 0x1FFFC000, val[3];
int count = 0, readcount = 1;
switch (t->idcode) {
case ID_STM32F72X: /* STM32F72|3 */
readcount++;
/* fall through.*/
case ID_STM32F74X:
case ID_STM32F76X:
/* F7 Devices have option bytes at 0x1FFF0000. */
start = 0x1FFF0000;
readcount++;
break;
case ID_STM32F42X:
case ID_STM32F46X:
readcount++;
}
if ((argc == 2) && !strcmp(argv[1], "erase")) {
stm32f4_option_write_default(t);
}
else if ((argc > 1) && !strcmp(argv[1], "write")) {
val[0] = strtoul(argv[2], NULL, 0);
count++;
if (argc > 2) {
val[1] = strtoul(argv[3], NULL, 0);
count ++;
}
if (argc > 3) {
val[2] = strtoul(argv[4], NULL, 0);
count ++;
}
if (optcr_mask(t, val))
stm32f4_option_write(t, val, count);
else
tc_printf(t, "error\n");
} else {
tc_printf(t, "usage: monitor option erase\n");
tc_printf(t, "usage: monitor option write <OPTCR>");
if (readcount > 1)
tc_printf(t, " <OPTCR1>");
if (readcount > 2)
tc_printf(t, " <OPTCR2>");
tc_printf(t, "\n");
}
val[0] = (target_mem_read32(t, start + 8) & 0xffff) << 16;
val[0] |= (target_mem_read32(t, start ) & 0xffff);
if (readcount > 1) {
if (start == 0x1FFFC000) /* F4 */ {
val[1] = target_mem_read32(t, start + 8 - 0x10000);
val[1] &= 0xffff;
} else {
val[1] = (target_mem_read32(t, start + 0x18) & 0xffff) << 16;
val[1] |= (target_mem_read32(t, start + 0x10) & 0xffff);
}
}
if (readcount > 2) {
val[2] = (target_mem_read32(t, start + 0x28) & 0xffff) << 16;
val[2] |= (target_mem_read32(t, start + 0x20) & 0xffff);
}
optcr_mask(t, val);
tc_printf(t, "OPTCR: 0x%08X ", val[0]);
if (readcount > 1)
tc_printf(t, "OPTCR1: 0x%08X ", val[1]);
if (readcount > 2)
tc_printf(t, "OPTCR2: 0x%08X" , val[2]);
tc_printf(t, "\n");
return true;
}