// Configure Timers
void configure_timers()
{
timer_port *timer2 = timer_dev_table[TIMER2].base;
timer_port *timer3 = timer_dev_table[TIMER3].base;
timer_port *timer4 = timer_dev_table[TIMER4].base;
stop_timers();
// Timer2
Timer2.setPrescaleFactor(CLOCK_FREQUENCY / (PHASE_COUNT * BASE_FREQUENCY));
Timer2.setOverflow(TIMER_COUNT - 1);
// Timer2 is configured as a master
timer2->CR2 |= (1 << 4);
// Timer3 */
Timer3.setPrescaleFactor(CLOCK_FREQUENCY / (PHASE_COUNT * BASE_FREQUENCY));
Timer3.setOverflow(TIMER_COUNT - 1);
// Connect timer3 to timer2 (ITR1), trigger mode
timer3->SMCR = (1 << 4) | 6;
// Timer4 */
Timer4.setPrescaleFactor(CLOCK_FREQUENCY / (PHASE_COUNT * BASE_FREQUENCY));
Timer4.setOverflow(TIMER_COUNT - 1);
// Connect timer4 to timer2 (ITR1), trigger mode
timer4->SMCR = (1 << 4) | 6;
// Initialize the Timer Channels
for(int x = 0; x < CHANNEL_COUNT; ++x)
{
TimerChannels[x].init(ChannelMap + x);
}
}
static void set_md_dul_throttle(int level) // level 1~10, 1: unlimit for 1s and zero for 9s, ..., 10: unlimit
{
TM_DBG_LOG("set_md_dul_throttle %d\n", level);
if (level >=1 && level < 10)
{
level_timeout = level;
reset_timers();
}
else if (level == 10)
{
set_md_ul_throttle(-1);
stop_timers();
}
else
TM_INFO_LOG("invalid level %d, ignored\n", level);
// if 10 set unlimit and stop timer
// if timer not created, create timer
// if timer created, reset timer
// unlimit ul, and start timer for level s
// when times out, limit ul to 1kbps, and start timer for 10 - level s
}
void M2MReportHandler::set_under_observation(bool observed)
{
tr_debug("M2MReportHandler::set_under_observation(observed %d)", (int)observed);
_under_observation = observed;
_report_scheduled = false;
stop_timers();
if(observed) {
handle_timers();
}
else {
set_default_values();
}
}
static int tx09_fb_release(struct fb_info *info, int user)
{
unsigned long flags;
pr_debug("%s\n", __func__);
spin_lock_irqsave(&tx09_lock, flags);
tx09_open_cnt--;
tx09_mmap = 0;
spin_unlock_irqrestore(&tx09_lock, flags);
if (tx09_open_cnt <= 0) {
stop_timers();
WRITE_PPI_CONTROL(0);
SSYNC();
disable_dma(CH_PPI);
}
return 0;
}
