void storage_alloc(storage_t *st, size_t n, at *init)
{
char _errmsg[200], *errmsg = &_errmsg[0];
ifn (st->data == NULL)
RAISEF("storage must be unsized", st->backptr);
/* allocate memory and initialize srg */
size_t s = n*storage_sizeof[st->type];
void *data = NULL;
if (st->type==ST_AT || st->type==ST_MPTR)
data = mm_malloc(mt_refs, s);
else
data = mm_malloc(mt_blob, s);
if (!data) {
sprintf(errmsg, "not enough memory for storage of size %.1f MByte", ((double)s)/(2<<20));
RAISEF(errmsg, NIL);
}
st->data = data;
st->kind = STS_MANAGED;
st->size = n;
/* clear gptr storage data (ATs and MPTRs are cleared by mm) */
if (init && n>0)
storage_clear(st, init, 0);
else if (st->type == ST_GPTR) {
gptr *pt = st->data;
for (int i=0; i<n; i++)
pt[i] = NULL;
}
}
void storage_realloc(storage_t *st, size_t size, at *init)
{
if (size < st->size)
RAISEF("storage size cannot be reduced", st->backptr);
size_t s = size*storage_sizeof[st->type];
size_t olds = st->size*storage_sizeof[st->type];
gptr olddata = st->data;
if (st->kind == STS_NULL) {
/* empty storage */
assert(st->data == NULL);
storage_alloc(st, size, init);
return;
} else {
/* reallocate memory and update srg */
if (st->kind == STS_MANAGED)
MM_ANCHOR(olddata);
if (st->type==ST_AT || st->type==ST_MPTR)
st->data = mm_allocv(mt_refs, s);
else
st->data = mm_blob(s);
if (st->data) {
memcpy(st->data, olddata, olds);
st->kind = STS_MANAGED;
}
}
if (st->data == NULL) {
st->data = olddata;
RAISEF("not enough memory", NIL);
}
size_t oldsize = st->size;
st->size = size;
if (init) {
/* temporarily clear read only flag to allow initialization */
bool isreadonly = st->isreadonly;
storage_clear(st, init, oldsize);
st->isreadonly = isreadonly;
}
}
int coreneuron10_cstep_execute(int argc, char * const argv[]) {
struct input_parameters p;
int error = MAPP_OK;
error = cstep_help(argc, argv, &p);
if(error != MAPP_OK)
return error;
//Gets the data
NrnThread * nt = (NrnThread *) storage_get(p.name, make_nrnthread, p.d, free_nrnthread);
if(nt == NULL){
storage_clear(p.name);
return MAPP_BAD_DATA;
}
//Initial mechanisms set-up already done in the input date (no need to call mech_init_Ih, etc)
gettimeofday(&tvBegin, NULL);
//Load mechanisms
mech_current_NaTs2_t(nt,&(nt->ml[17]));
mech_current_Ih(nt,&(nt->ml[10]));
mech_current_ProbAMPANMDA_EMS(nt,&(nt->ml[18]));
//Call solver
nrn_solve_minimal(nt);
//Update the states
mech_state_NaTs2_t(nt,&(nt->ml[17]));
mech_state_Ih(nt,&(nt->ml[10]));
mech_state_ProbAMPANMDA_EMS(nt,&(nt->ml[18]));
gettimeofday(&tvEnd, NULL);
timeval_subtract(&tvDiff, &tvEnd, &tvBegin);
printf("\nTime for full computational step: %ld [s] %ld [us]\n", tvDiff.tv_sec, (long) tvDiff.tv_usec);
return error;
}
/*-------------------------------------------------------------------*/
int ARCH_DEP(system_reset) (const int cpu, const int clear, const int target_mode)
{
int rc;
int n;
int regs_mode;
int architecture_switch;
REGS* regs;
CPU_BITMAP mask;
/* Configure the cpu if it is not online (configure implies initial
* reset)
*/
if (!IS_CPU_ONLINE(cpu))
{
sysblk.arch_mode = target_mode;
if ( (rc = configure_cpu(cpu)) )
return rc;
}
HDC1(debug_cpu_state, sysblk.regs[cpu]);
/* Define the target mode for reset */
if (target_mode > ARCH_390 &&
(clear || sysblk.arch_mode != target_mode))
regs_mode = ARCH_390;
else
regs_mode = target_mode;
architecture_switch = (target_mode != sysblk.arch_mode);
/* Signal all CPUs in configuration to stop and reset */
{
/* Switch lock context to hold both sigplock and intlock */
RELEASE_INTLOCK(NULL);
obtain_lock(&sysblk.sigplock);
OBTAIN_INTLOCK(NULL);
/* Ensure no external updates pending */
OFF_IC_SERVSIG;
OFF_IC_INTKEY;
/* Loop through CPUs and issue appropriate CPU reset function
*/
{
mask = sysblk.config_mask;
for (n = 0; mask; mask >>= 1, ++n)
{
if (mask & 1)
{
regs = sysblk.regs[n];
/* Signal CPU reset function; if requesting CPU with
* CLEAR or architecture change, signal initial CPU
* reset. Otherwise, signal a normal CPU reset.
*/
regs->arch_mode = regs_mode;
if (n == cpu &&
(clear || architecture_switch))
regs->sigpireset = 1;
else
regs->sigpreset = 1;
regs->opinterv = 1;
regs->cpustate = CPUSTATE_STOPPING;
ON_IC_INTERRUPT(regs);
wakeup_cpu(regs);
}
}
}
/* Return to hold of just intlock */
RELEASE_INTLOCK(NULL);
release_lock(&sysblk.sigplock);
OBTAIN_INTLOCK(NULL);
}
/* Wait for CPUs to complete reset */
{
int i;
int wait;
for (n = 0; ; ++n)
{
mask = sysblk.config_mask;
for (i = wait = 0; mask; mask >>= 1, ++i)
{
regs = sysblk.regs[i];
if (regs->cpustate != CPUSTATE_STOPPED)
{
/* Release intlock, take a nap, and re-acquire */
RELEASE_INTLOCK(NULL);
wait = 1;
usleep(10000);
OBTAIN_INTLOCK(NULL);
}
}
if (!wait)
break;
if (n < 300)
continue;
/* FIXME: Recovery code needed to handle case where CPUs
* are misbehaving. Outstanding locks should be
* reported, then take-over CPUs and perform an
* initial reset of each CPU.
*/
WRMSG(HHC90000, "E", "Could not perform reset within three seconds");
break;
}
}
/* Perform subsystem reset */
subsystem_reset();
/* Switch modes to requested mode */
sysblk.arch_mode = regs_mode;
/* Perform system-reset-clear additional functions */
if (clear)
{
/* Finish reset-clear of all CPUs in the configuration */
for (n = 0; n < sysblk.maxcpu; ++n)
{
if (IS_CPU_ONLINE(n))
{
regs = sysblk.regs[n];
/* Clear all the registers (AR, GPR, FPR, VR) as part
* of the CPU CLEAR RESET operation
*/
memset (regs->ar, 0, sizeof(regs->ar));
memset (regs->gr, 0, sizeof(regs->gr));
memset (regs->fpr, 0, sizeof(regs->fpr));
#if defined(_FEATURE_VECTOR_FACILITY)
memset (regs->vf->vr, 0, sizeof(regs->vf->vr));
#endif /*defined(_FEATURE_VECTOR_FACILITY)*/
}
}
sysblk.ipled = FALSE;
sysblk.program_parameter = 0;
/* Clear storage */
sysblk.main_clear = sysblk.xpnd_clear = 0;
storage_clear();
xstorage_clear();
}
#if defined(FEATURE_CONFIGURATION_TOPOLOGY_FACILITY)
/* Clear topology-change-report-pending condition */
sysblk.topchnge = 0;
#endif /*defined(FEATURE_CONFIGURATION_TOPOLOGY_FACILITY)*/
/* set default system state to reset */
sysblk.sys_reset = TRUE;
return (0);
} /* end function system_reset */
/*-------------------------------------------------------------------*/
int ARCH_DEP(system_reset) (int cpu, int clear)
{
int rc1 = 0, rc;
int n;
REGS *regs;
/* Configure the cpu if it is not online (configure implies init reset) */
if (!IS_CPU_ONLINE(cpu))
if ( (rc = configure_cpu(cpu)) )
return rc;
HDC1(debug_cpu_state, sysblk.regs[cpu]);
/* Reset external interrupts */
OFF_IC_SERVSIG;
OFF_IC_INTKEY;
/* Perform system-reset-normal or system-reset-clear function */
if (clear)
{
/* Reset all CPUs in the configuration */
for (n = 0; n < sysblk.maxcpu; n++)
if (IS_CPU_ONLINE(n))
{
regs=sysblk.regs[n];
if ((rc = ARCH_DEP(initial_cpu_reset) (regs)) )
rc1 = rc;
else
{
/* Clear all the registers (AR, GPR, FPR, VR)
as part of the CPU CLEAR RESET operation */
memset (regs->ar, 0, sizeof(regs->ar));
memset (regs->gr, 0, sizeof(regs->gr));
memset (regs->fpr, 0, sizeof(regs->fpr));
#if defined(_FEATURE_VECTOR_FACILITY)
memset (regs->vf->vr, 0, sizeof(regs->vf->vr));
#endif /*defined(_FEATURE_VECTOR_FACILITY)*/
}
}
sysblk.program_parameter = 0;
/* Clear storage */
sysblk.main_clear = sysblk.xpnd_clear = 0;
storage_clear();
xstorage_clear();
}
else
{
/* Reset all CPUs in the configuration */
for (n = 0; n < sysblk.maxcpu; n++)
if (IS_CPU_ONLINE(n))
{
regs=sysblk.regs[n];
if(n == cpu)
{
/* Perform initial reset on the IPL CPU */
if ( (rc = ARCH_DEP(initial_cpu_reset) (regs)) )
rc1 = rc;
}
else
{
/* Perform reset on the other CPUs */
if ( (rc = ARCH_DEP(cpu_reset) (regs)) )
rc1 = rc;
}
}
}
/* Perform I/O subsystem reset */
io_reset ();
#if defined(FEATURE_CONFIGURATION_TOPOLOGY_FACILITY)
/* Clear topology-change-report-pending condition */
sysblk.topchnge = 0;
#endif /*defined(FEATURE_CONFIGURATION_TOPOLOGY_FACILITY)*/
/* set default system state to reset */
sysblk.sys_reset = TRUE;
return rc1;
} /* end function system_reset */
/*-------------------------------------------------------------------*/
int ARCH_DEP(system_reset)
(
const int cpu, /* CPU address */
const int flags, /* Flags:
* 0x00 0000 0000 System reset normal
* 0x01 .... ...1 System reset clear
* 0x02 .... ..1. System reset normal
* with initial CPU
* reset on requesting
* processor (used by
* IPL)
*/
const int target_mode /* Target architecture mode */
)
{
int rc;
int n;
int regs_mode;
int architecture_switch;
REGS* regs;
CPU_BITMAP mask;
/* Configure the cpu if it is not online (configure implies initial
* reset)
*/
if (!IS_CPU_ONLINE(cpu))
{
sysblk.arch_mode = target_mode;
if ( (rc = configure_cpu(cpu)) )
return rc;
}
HDC1(debug_cpu_state, sysblk.regs[cpu]);
/* Define the target mode for reset */
if (flags &&
target_mode > ARCH_390)
regs_mode = ARCH_390;
else
regs_mode = target_mode;
architecture_switch = (regs_mode != sysblk.arch_mode);
/* Signal all CPUs in configuration to stop and reset */
{
/* Switch lock context to hold both sigplock and intlock */
RELEASE_INTLOCK(NULL);
obtain_lock(&sysblk.sigplock);
OBTAIN_INTLOCK(NULL);
/* Ensure no external updates pending */
OFF_IC_SERVSIG;
OFF_IC_INTKEY;
/* Loop through CPUs and issue appropriate CPU reset function
*/
{
mask = sysblk.config_mask;
for (n = 0; mask; mask >>= 1, ++n)
{
if (mask & 1)
{
regs = sysblk.regs[n];
/* Signal CPU reset function; if requesting CPU with
* CLEAR or architecture change, signal initial CPU
* reset. Otherwise, signal a normal CPU reset.
*/
if ((n == cpu && (flags & 0x03)) ||
architecture_switch)
regs->sigpireset = 1;
else
regs->sigpreset = 1;
regs->opinterv = 1;
regs->cpustate = CPUSTATE_STOPPING;
ON_IC_INTERRUPT(regs);
wakeup_cpu(regs);
}
}
}
/* Return to hold of just intlock */
RELEASE_INTLOCK(NULL);
release_lock(&sysblk.sigplock);
OBTAIN_INTLOCK(NULL);
}
/* Wait for CPUs to complete reset */
{
int i;
int wait;
for (n = 0; ; ++n)
{
mask = sysblk.config_mask;
for (i = wait = 0; mask; mask >>= 1, ++i)
{
if (!(mask & 1))
continue;
regs = sysblk.regs[i];
if (regs->cpustate != CPUSTATE_STOPPED)
{
/* Release intlock, take a nap, and re-acquire */
RELEASE_INTLOCK(NULL);
wait = 1;
usleep(10000);
OBTAIN_INTLOCK(NULL);
}
}
if (!wait)
break;
if (n < 300)
continue;
/* FIXME: Recovery code needed to handle case where CPUs
* are misbehaving. Outstanding locks should be
* reported, then take-over CPUs and perform an
* initial reset of each CPU.
*/
WRMSG(HHC90000, "E", "Could not perform reset within three seconds");
break;
}
}
/* If architecture switch, complete reset in requested mode */
if (architecture_switch)
{
sysblk.arch_mode = regs_mode;
return ARCH_DEP(system_reset)(cpu, flags, target_mode);
}
/* Perform subsystem reset
*
* GA22-7000-10 IBM System/370 Principles of Operation, Chapter 4.
* Control, Subsystem Reset, p. 4-34
* SA22-7085-00 IBM System/370 Extended Architecture Principles of
* Operation, Chapter 4. Control, Subsystem Reset,
* p. 4-28
* SA22-7832-09 z/Architecture Principles of Operation, Chapter 4.
* Control, Subsystem Reset, p. 4-57
*/
subsystem_reset();
/* Perform system-reset-clear additional functions */
if (flags & 0x01)
{
/* Finish reset-clear of all CPUs in the configuration */
for (n = 0; n < sysblk.maxcpu; ++n)
{
if (IS_CPU_ONLINE(n))
{
regs = sysblk.regs[n];
/* Clear all the registers (AR, GPR, FPR, VR) as part
* of the CPU CLEAR RESET operation
*/
memset (regs->ar, 0, sizeof(regs->ar));
memset (regs->gr, 0, sizeof(regs->gr));
memset (regs->fpr, 0, sizeof(regs->fpr));
#if defined(_FEATURE_VECTOR_FACILITY)
memset (regs->vf->vr, 0, sizeof(regs->vf->vr));
#endif /*defined(_FEATURE_VECTOR_FACILITY)*/
/* Clear the instruction counter and CPU time used */
cpu_reset_instcount_and_cputime(regs);
}
}
/* Clear storage */
sysblk.main_clear = sysblk.xpnd_clear = 0;
storage_clear();
xstorage_clear();
/* Clear IPL program parameter */
sysblk.program_parameter = 0;
}
/* If IPL call, reset CPU instruction counts and times */
else if (flags & 0x02)
{
CPU_BITMAP mask = sysblk.config_mask;
int i;
for (i = 0; mask; mask >>= 1, ++i)
{
if (mask & 1)
cpu_reset_instcount_and_cputime(sysblk.regs[i]);
}
}
/**@snippet [Handling the data received over BLE] */
static void nus_data_handler(ble_nus_t * p_nus, uint8_t * p_data, uint16_t length)
{
uint32_t err_code;
if (length==1) //< Control Command
{
switch(p_data[0])
{
/** Radio transmit power in dBm
* (accepted values are -40, -30, -20, -16, -12, -8, -4, 0, and 4 dBm). */
case '1':
err_code = ble_nus_string_send(p_nus, (uint8_t *) "Power set to -40", 16);
APP_ERROR_CHECK(err_code);
gap_tx_power = -40;
err_code = sd_ble_gap_tx_power_set(gap_tx_power);
APP_ERROR_CHECK(err_code);
break;
case '2':
err_code = ble_nus_string_send(p_nus, (uint8_t *) "Power set to -20", 16);
APP_ERROR_CHECK(err_code);
gap_tx_power = -20;
err_code = sd_ble_gap_tx_power_set(gap_tx_power);
APP_ERROR_CHECK(err_code);
break;
case '3':
err_code = ble_nus_string_send(p_nus, (uint8_t *) "Power set to 0", 14);
APP_ERROR_CHECK(err_code);
gap_tx_power = 0;
err_code = sd_ble_gap_tx_power_set(gap_tx_power);
APP_ERROR_CHECK(err_code);
break;
case 'c':
;
storage_clear();
err_code = ble_nus_string_send(p_nus, (uint8_t *) "Storage cleared.", 16);
APP_ERROR_CHECK(err_code);
break;
case 'l':
;
char str_l[17];
sprintf(str_l, "Toggled lock to %d", storage_toggle_lock());
ble_nus_string_send(p_nus, (uint8_t *) str_l, 18);
break;
case 'r':
store_read_init();
read_store_data(m_nus_data, &m_data_length);
nrf_delay_ms(MAX_CONN_INTERVAL * 2);
m_file_in_transit = true;
err_code = ble_nus_string_send(p_nus, (uint8_t *) "***DATA TRANSFER***", 19);
APP_ERROR_CHECK(err_code);
break;
case 't':
;
char str_t[20];
uint8_t c;
uint32_t ts = NRF_RTC1->COUNTER;
c = sprintf(str_t, "ts:%lu epoch:%d", ts, timer_epoch);
err_code = ble_nus_string_send(p_nus, (uint8_t *) str_t, c);
APP_ERROR_CHECK(err_code);
break;
}
}
__LOG("NUSCON:%s", p_data);
}
/*-------------------------------------------------------------------*/
int ARCH_DEP(system_reset) (int cpu, int clear)
{
int rc = 0;
REGS *regs;
/* Configure the cpu if it is not online */
if (!IS_CPU_ONLINE(cpu))
{
if (configure_cpu(cpu) != 0)
{
/* ZZ FIXME: we should probably present a machine-check
if we encounter any errors during the reset (rc != 0) */
return -1;
}
ASSERT(IS_CPU_ONLINE(cpu));
}
regs = sysblk.regs[cpu];
HDC1(debug_cpu_state, regs);
/* Perform system-reset-normal or system-reset-clear function */
if (!clear)
{
/* Reset external interrupts */
OFF_IC_SERVSIG;
OFF_IC_INTKEY;
/* Reset all CPUs in the configuration */
for (cpu = 0; cpu < MAX_CPU; cpu++)
if (IS_CPU_ONLINE(cpu))
if (ARCH_DEP(cpu_reset) (sysblk.regs[cpu]))
rc = -1;
/* Perform I/O subsystem reset */
io_reset ();
}
else
{
/* Reset external interrupts */
OFF_IC_SERVSIG;
OFF_IC_INTKEY;
/* Reset all CPUs in the configuration */
for (cpu = 0; cpu < MAX_CPU; cpu++)
{
if (IS_CPU_ONLINE(cpu))
{
regs=sysblk.regs[cpu];
if (ARCH_DEP(initial_cpu_reset) (regs))
{
rc = -1;
}
/* Clear all the registers (AR, GPR, FPR, VR)
as part of the CPU CLEAR RESET operation */
memset (regs->ar,0,sizeof(regs->ar));
memset (regs->gr,0,sizeof(regs->gr));
memset (regs->fpr,0,sizeof(regs->fpr));
#if defined(_FEATURE_VECTOR_FACILITY)
memset (regs->vf->vr,0,sizeof(regs->vf->vr));
#endif /*defined(_FEATURE_VECTOR_FACILITY)*/
}
}
/* Perform I/O subsystem reset */
io_reset ();
/* Clear storage */
sysblk.main_clear = sysblk.xpnd_clear = 0;
storage_clear();
xstorage_clear();
}
#if defined(FEATURE_CONFIGURATION_TOPOLOGY_FACILITY)
/* Clear topology-change-report-pending condition */
sysblk.topchnge = 0;
#endif /*defined(FEATURE_CONFIGURATION_TOPOLOGY_FACILITY)*/
/* ZZ FIXME: we should probably present a machine-check
if we encounter any errors during the reset (rc != 0) */
return rc;
} /* end function system_reset */
