Beispiel #1
0
/*
 * Check board identity.  Always successful (gives information only)
 */
int checkboard (void)
{
	DECLARE_GLOBAL_DATA_PTR;

	char *s;
	char buf[64];
	int i;

	i = getenv_r ("board_id", buf, sizeof (buf));
	s = (i > 0) ? buf : NULL;

	if (s) {
		printf ("%s ", s);
	} else {
		printf ("<unknown> ");
	}

	i = getenv_r ("serial#", buf, sizeof (buf));
	s = (i > 0) ? buf : NULL;

	if (s) {
		printf ("S/N %s\n", s);
	} else {
		printf ("S/N <unknown>\n");
	}

	printf ("CPU at %s MHz, ", strmhz (buf, gd->cpu_clk));
	printf ("local bus at %s MHz\n", strmhz (buf, gd->bus_clk));
	return (0);
}
Beispiel #2
0
phys_size_t fixed_sdram(void)
{
	int i;
	char buf[32];
	fsl_ddr_cfg_regs_t ddr_cfg_regs;
	phys_size_t ddr_size;
	ulong ddr_freq, ddr_freq_mhz;

	ddr_freq = get_ddr_freq(0);
	ddr_freq_mhz = ddr_freq / 1000000;

	printf("Configuring DDR for %s MT/s data rate\n",
	       strmhz(buf, ddr_freq));

	for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
		if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
		    (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
			memcpy(&ddr_cfg_regs,
			       fixed_ddr_parm_0[i].ddr_settings,
			       sizeof(ddr_cfg_regs));
			break;
		}
	}

	if (fixed_ddr_parm_0[i].max_freq == 0)
		panic("Unsupported DDR data rate %s MT/s data rate\n",
		      strmhz(buf, ddr_freq));

	ddr_size = (phys_size_t)2048 * 1024 * 1024;
	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);

	return ddr_size;
}
Beispiel #3
0
/*
 * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
 * determine which one we are running on, based on the Chip Identification
 * Register (CIR).
 */
int print_cpuinfo(void)
{
	char buf[32];
	unsigned short cir;	/* Chip Identification Register */
	unsigned short pin;	/* Part identification number */
	unsigned char prn;	/* Part revision number */
	char *cpu_model;

	cir = mbar_readShort(MCF_CCM_CIR);
	pin = cir >> MCF_CCM_CIR_PIN_LEN;
	prn = cir & MCF_CCM_CIR_PRN_MASK;

	switch (pin) {
	case MCF_CCM_CIR_PIN_MCF5270:
		cpu_model = "5270";
		break;
	case MCF_CCM_CIR_PIN_MCF5271:
		cpu_model = "5271";
		break;
	default:
		cpu_model = NULL;
		break;
	}

	if (cpu_model)
		printf("CPU:   Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
		       cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK));
	else
		printf("CPU:   Unknown - Freescale ColdFire MCF5271 family"
		       " (PIN: 0x%x) rev. %hu, at %s MHz\n",
		       pin, prn, strmhz(buf, CONFIG_SYS_CLK));

	return 0;
}
int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	bd_t *bd = gd->bd;
	char buf[32];

	printf("U-Boot      = %s\n", bd->bi_r_version);
	printf("CPU         = %s\n", bd->bi_cpu);
	printf("Board       = %s\n", bd->bi_board_name);
	print_str("VCO",         strmhz(buf, bd->bi_vco));
	print_str("CCLK",        strmhz(buf, bd->bi_cclk));
	print_str("SCLK",        strmhz(buf, bd->bi_sclk));

	print_num("boot_params", (ulong)bd->bi_boot_params);
	print_num("memstart",    (ulong)bd->bi_memstart);
	print_lnum("memsize",    (u64)bd->bi_memsize);
	print_num("flashstart",  (ulong)bd->bi_flashstart);
	print_num("flashsize",   (ulong)bd->bi_flashsize);
	print_num("flashoffset", (ulong)bd->bi_flashoffset);

	print_eth(0);
	printf("ip_addr     = %pI4\n", &bd->bi_ip_addr);
	printf("baudrate    = %d bps\n", bd->bi_baudrate);

	return 0;
}
int checkboard (void)
{
	sys_info_t sysinfo;
	char buf[32];

	get_sys_info (&sysinfo);

#ifdef CONFIG_SBC8560
	printf ("Board: Wind River SBC8560 Board\n");
#else
	printf ("Board: Wind River SBC8540 Board\n");
#endif
	printf ("\tCPU: %s MHz\n", strmhz(buf, sysinfo.freqProcessor[0]));
	printf ("\tCCB: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus));
	printf ("\tDDR: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus/2));
	if((CONFIG_SYS_LBC_LCRR & 0x0f) == 2 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 4 \
		|| (CONFIG_SYS_LBC_LCRR & 0x0f) == 8) {
		printf ("\tLBC: %s MHz\n",
			strmhz(buf, sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f)));
	} else {
		printf("\tLBC: unknown\n");
	}
	printf("\tCPM: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus));
	printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
	return (0);
}
Beispiel #6
0
int checkcpu(void)
{
	siu_t *siu = (siu_t *) MMAP_SIU;
	u16 id = 0;

	puts("CPU:   ");

	switch ((in_be32(&siu->jtagid) & 0x000FF000) >> 12) {
	case 0x0C:
		id = 5485;
		break;
	case 0x0D:
		id = 5484;
		break;
	case 0x0E:
		id = 5483;
		break;
	case 0x0F:
		id = 5482;
		break;
	case 0x10:
		id = 5481;
		break;
	case 0x11:
		id = 5480;
		break;
	case 0x12:
		id = 5475;
		break;
	case 0x13:
		id = 5474;
		break;
	case 0x14:
		id = 5473;
		break;
	case 0x15:
		id = 5472;
		break;
	case 0x16:
		id = 5471;
		break;
	case 0x17:
		id = 5470;
		break;
	}

	if (id) {
		char buf1[32], buf2[32];

		printf("Freescale MCF%d\n", id);
		printf("       CPU CLK %s MHz BUS CLK %s MHz\n",
		       strmhz(buf1, gd->cpu_clk),
		       strmhz(buf2, gd->bus_clk));
	}

	return 0;
};
Beispiel #7
0
int print_cpuinfo(void)
{
	char buf1[32], buf2[32];

	printf("CPU:   Freescale Coldfire MCF5208\n"
	       "       CPU CLK %s MHz BUS CLK %s MHz\n",
	       strmhz(buf1, gd->cpu_clk),
	       strmhz(buf2, gd->bus_clk));
	return 0;
};
Beispiel #8
0
phys_size_t fixed_sdram(void)
{
    int i;
    char buf[32];
    fsl_ddr_cfg_regs_t ddr_cfg_regs;
    phys_size_t ddr_size;
    unsigned int lawbar1_target_id;
    ulong ddr_freq, ddr_freq_mhz;

    ddr_freq = get_ddr_freq(0);
    ddr_freq_mhz = ddr_freq / 1000000;

    printf("Configuring DDR for %s MT/s data rate\n",
           strmhz(buf, ddr_freq));

    for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
        if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
                (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
            memcpy(&ddr_cfg_regs,
                   fixed_ddr_parm_0[i].ddr_settings,
                   sizeof(ddr_cfg_regs));
            break;
        }
    }

    if (fixed_ddr_parm_0[i].max_freq == 0)
        panic("Unsupported DDR data rate %s MT/s data rate\n",
              strmhz(buf, ddr_freq));

    ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
    ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
    fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);

    /*
     * setup laws for DDR. If not interleaving, presuming half memory on
     * DDR1 and the other half on DDR2
     */
    if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) {
        if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
                         ddr_size,
                         LAW_TRGT_IF_DDR_INTRLV) < 0) {
            printf("ERROR setting Local Access Windows for DDR\n");
            return 0;
        }
    } else {
        lawbar1_target_id = LAW_TRGT_IF_DDR_1;
        if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
                         ddr_size,
                         lawbar1_target_id) < 0) {
            printf("ERROR setting Local Access Windows for DDR\n");
            return 0;
        }
    }
    return ddr_size;
}
Beispiel #9
0
int prt_mpc5xxx_clks (void)
{
    char buf1[32], buf2[32], buf3[32];

    printf ("       Bus %s MHz, IPB %s MHz, PCI %s MHz\n",
            strmhz(buf1, gd->bus_clk),
            strmhz(buf2, gd->arch.ipb_clk),
            strmhz(buf3, gd->pci_clk)
           );
    return (0);
}
Beispiel #10
0
int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
	char buf[32];

	printf("Clock configuration:\n");
	printf("  CPU:                 %-4s MHz\n", strmhz(buf, gd->cpu_clk));
	printf("  Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk));
	printf("  IPS Bus:             %-4s MHz\n", strmhz(buf, gd->ips_clk));
	printf("  PCI:                 %-4s MHz\n", strmhz(buf, gd->pci_clk));
	printf("  DDR:                 %-4s MHz\n", strmhz(buf, 2*gd->csb_clk));
	return 0;
}
Beispiel #11
0
int print_cpuinfo(void)
{
	char buf[32];

	printf("CPU: %s\n", AT91_CPU_NAME);
	printf("Crystal frequency: %8s MHz\n",
					strmhz(buf, get_main_clk_rate()));
	printf("CPU clock        : %8s MHz\n",
					strmhz(buf, get_cpu_clk_rate()));
	printf("Master clock     : %8s MHz\n",
					strmhz(buf, get_mck_clk_rate()));

	return 0;
}
Beispiel #12
0
void lcd_show_board_info(void)
{
	ulong dram_size;
	uint64_t nand_size;
	int i;
	char temp[32];

	lcd_printf("%s\n", U_BOOT_VERSION);
	lcd_printf("(C) 2013 ATMEL Corp\n");
	lcd_printf("[email protected]\n");
	lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
		   strmhz(temp, get_cpu_clk_rate()));

	dram_size = 0;
	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
		dram_size += gd->bd->bi_dram[i].size;

	nand_size = 0;
#ifdef CONFIG_NAND_ATMEL
	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
		nand_size += nand_info[i]->size;
#endif
	lcd_printf("%ld MB SDRAM, %lld MB NAND\n",
		   dram_size >> 20, nand_size >> 20);
}
int print_cpuinfo(void)
{
	char mhz[8];

	printf("CPU:   ARC EM9D at %s MHz\n", strmhz(mhz, gd->cpu_clk));
	return 0;
}
Beispiel #14
0
/*
 * Print the CPU specific information
 */
int print_cpuinfo(void)
{
	char	buf[4][32];

	printf("CPU  : %s\n", "STM32F103ZET (Cortex-M3)");


	strmhz(buf[0], clock_get(CLOCK_SYSCLK));
	strmhz(buf[1], clock_get(CLOCK_HCLK));
	strmhz(buf[2], clock_get(CLOCK_PCLK1));
	strmhz(buf[3], clock_get(CLOCK_PCLK2));
	printf("Freqs: SYSCLK=%sMHz,HCLK=%sMHz,PCLK1=%sMHz,PCLK2=%sMHz\n",
		buf[0], buf[1], buf[2], buf[3]);

	return 0;
}
Beispiel #15
0
void lcd_show_board_info(void)
{
	ulong dram_size, nand_size;
	int i;
	char temp[32];

	if (has_lcdc()) {
		lcd_printf("%s\n", U_BOOT_VERSION);
		lcd_printf("(C) 2012 ATMEL Corp\n");
		lcd_printf("[email protected]\n");
		lcd_printf("%s CPU at %s MHz\n",
			get_cpu_name(),
			strmhz(temp, get_cpu_clk_rate()));

		dram_size = 0;
		for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
			dram_size += gd->bd->bi_dram[i].size;
		nand_size = 0;
		for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
			nand_size += get_nand_dev_by_index(i)->size;
		lcd_printf("  %ld MB SDRAM, %ld MB NAND\n",
			dram_size >> 20,
			nand_size >> 20);
	}
}
Beispiel #16
0
__maybe_unused
static void print_mhz(const char *name, unsigned long hz)
{
	char buf[32];

	printf("%-12s= %6s MHz\n", name, strmhz(buf, hz));
}
Beispiel #17
0
phys_size_t fixed_sdram (void)
{
    char buf[32];
    fsl_ddr_cfg_regs_t ddr_cfg_regs;
    size_t ddr_size;
    struct cpu_type *cpu;
    ulong ddr_freq, ddr_freq_mhz;

    cpu = gd->arch.cpu;
    /* P1020 and it's derivatives support max 32bit DDR width */
    if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
        ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
    } else {
        ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
    }
#if defined(CONFIG_SYS_RAMBOOT)
    return ddr_size;
#endif
    ddr_freq = get_ddr_freq(0);
    ddr_freq_mhz = ddr_freq / 1000000;

    printf("Configuring DDR for %s MT/s data rate\n",
           strmhz(buf, ddr_freq));

    if(ddr_freq_mhz <= 400)
        memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs));
    else if(ddr_freq_mhz <= 533)
        memcpy(&ddr_cfg_regs, &ddr_cfg_regs_533, sizeof(ddr_cfg_regs));
    else if(ddr_freq_mhz <= 667)
        memcpy(&ddr_cfg_regs, &ddr_cfg_regs_667, sizeof(ddr_cfg_regs));
    else if(ddr_freq_mhz <= 800)
        memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs));
    else
        panic("Unsupported DDR data rate %s MT/s data rate\n",
              strmhz(buf, ddr_freq));

    /* P1020 and it's derivatives support max 32bit DDR width */
    if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
        ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE;
        ddr_cfg_regs.cs[0].bnds = 0x0000001F;
    }

    fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);

    set_ddr_laws(0, ddr_size, LAW_TRGT_IF_DDR_1);
    return ddr_size;
}
Beispiel #18
0
/*
 * Print the CPU specific information
 */
int print_cpuinfo(void)
{
	char buf[2][32];

#if defined(CONFIG_SYS_ARMCORTEXM4)
	printf("CPU  : %s\n", "LPC43xx series (Cortex-M4/M0)");
#else
	printf("CPU  : %s\n", "LPC18xx series (Cortex-M3)");
#endif

	strmhz(buf[0], clock_get(CLOCK_SYSTICK));
	strmhz(buf[1], clock_get(CLOCK_CCLK));
	printf("Freqs: SYSTICK=%sMHz,CCLK=%sMHz\n",
		buf[0], buf[1]);

	return 0;
}
Beispiel #19
0
/*
 * Print the CPU specific information
 */
int print_cpuinfo(void)
{
	char	buf[5][32];

	printf("CPU  : %s\n", "SmartFusion FPGA (Cortex-M3 Hard IP)");

	strmhz(buf[0], clock_get(CLOCK_FCLK));
	strmhz(buf[1], clock_get(CLOCK_PCLK0));
	strmhz(buf[2], clock_get(CLOCK_PCLK1));
	strmhz(buf[3], clock_get(CLOCK_ACE));
	strmhz(buf[4], clock_get(CLOCK_FPGA));
	printf("Freqs: FCLK=%sMHz,PCLK0=%sMHz,PCLK1=%sMHz,ACE=%sMHz,"
		"FPGA=%sMHz\n",
		buf[0], buf[1], buf[2], buf[3], buf[4]);

	return 0;
}
Beispiel #20
0
int print_cpuinfo(void)
{
	char buf[32];

	printf("CPU:   Freescale Coldfire MCF5249 at %s MHz\n",
	       strmhz(buf, CONFIG_SYS_CLK));
	return 0;
}
int checkcpu(void)
{
	char buf[32];

	printf("CPU:   Freescale Coldfire MCF5275 at %s MHz\n",
			strmhz(buf, CONFIG_SYS_CLK));
	return 0;
};
Beispiel #22
0
int checkboard(void)
{
    ulong busfreq  = get_bus_freq(0);
    char  buf[32];

    puts ("Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B)\n");
    printf("Built: %s at %s\n", __DATE__ , __TIME__ );
    /* printf("MPLD:  Revision %d\n", SYS_REVID_GET()); */
    printf("Local Bus at %s MHz\n", strmhz(buf, busfreq));
    return 0;
}
static int video_show_board_logo_info(void)
{
	ulong dram_size, nand_size;
	int i;
	u32 len = 0;
	char buf[255];
	char *corp = "2017 Microchip Technology Inc.\n";
	char temp[32];
	struct udevice *dev, *con;
	const char *s;
	vidinfo_t logo_info;
	int ret;

	get_microchip_logo_info(&logo_info);

	len += sprintf(&buf[len], "%s\n", U_BOOT_VERSION);
	memcpy(&buf[len], corp, strlen(corp));
	len += strlen(corp);
	len += sprintf(&buf[len], "%s CPU at %s MHz\n", get_cpu_name(),
			strmhz(temp, get_cpu_clk_rate()));

	dram_size = 0;
	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
		dram_size += gd->bd->bi_dram[i].size;

	nand_size = 0;
#ifdef CONFIG_NAND_ATMEL
	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
		nand_size += nand_info[i]->size;
#endif

	len += sprintf(&buf[len], "%ld MB SDRAM, %ld MB NAND\n",
		       dram_size >> 20, nand_size >> 20);

	ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
	if (ret)
		return ret;

	ret = video_bmp_display(dev, logo_info.logo_addr,
				logo_info.logo_x_offset,
				logo_info.logo_y_offset, false);
	if (ret)
		return ret;

	ret = uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con);
	if (ret)
		return ret;

	vidconsole_position_cursor(con, 0, logo_info.logo_height);
	for (s = buf, i = 0; i < len; s++, i++)
		vidconsole_put_char(con, *s);

	return 0;
}
Beispiel #24
0
/* Fixed sdram init -- doesn't use serial presence detect. */
phys_size_t fixed_sdram(void)
{
	sys_info_t sysinfo;
	char buf[32];
	size_t ddr_size;
	fsl_ddr_cfg_regs_t ddr_cfg_regs = {
		.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
		.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
		.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
		.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
		.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
		.cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
#endif
		.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
		.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
		.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
		.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
		.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
		.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
		.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
		.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
		.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
		.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
		.ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
		.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
		.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
		.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
		.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
		.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
		.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
		.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
		.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
		.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
		.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
	};

	get_sys_info(&sysinfo);
	printf("Configuring DDR for %s MT/s data rate\n",
			strmhz(buf, sysinfo.freq_ddrbus));

	ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;

	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);

	if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
				ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
		printf("ERROR setting Local Access Windows for DDR\n");
		return 0;
	};

	return ddr_size;
}
Beispiel #25
0
/*
 * Fixed sdram init -- doesn't use serial presence detect.
 */
phys_size_t fixed_sdram(void)
{
	int i;
	char buf[32];
	fsl_ddr_cfg_regs_t ddr_cfg_regs;
	phys_size_t ddr_size;
	ulong ddr_freq, ddr_freq_mhz;
	struct cpu_type *cpu;

#if defined(CONFIG_SYS_RAMBOOT)
	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
#endif

	ddr_freq = get_ddr_freq(0);
	ddr_freq_mhz = ddr_freq / 1000000;

	printf("Configuring DDR for %s MT/s data rate\n",
				strmhz(buf, ddr_freq));

	for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
		if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
		   (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
			memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
							sizeof(ddr_cfg_regs));
			break;
		}
	}

	if (fixed_ddr_parm_0[i].max_freq == 0)
		panic("Unsupported DDR data rate %s MT/s data rate\n",
					strmhz(buf, ddr_freq));

	cpu = gd->cpu;
	/* P1014 and it's derivatives support max 16bit DDR width */
	if (cpu->soc_ver == SVR_P1014) {
		ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_16_BE;
		ddr_cfg_regs.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS >> 1;
		ddr_cfg_regs.ddr_sdram_cfg &= ~0x00180000;
		ddr_cfg_regs.ddr_sdram_cfg |= 0x001080000;
	}
phys_size_t fixed_sdram (void)
{
	sys_info_t sysinfo;
	char buf[32];
	fsl_ddr_cfg_regs_t ddr_cfg_regs;
	size_t ddr_size;
	struct cpu_type *cpu;

	get_sys_info(&sysinfo);
	printf("Configuring DDR for %s MT/s data rate\n",
				strmhz(buf, sysinfo.freqDDRBus));

	if(sysinfo.freqDDRBus <= DATARATE_400MHZ)
		memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs));
	else if(sysinfo.freqDDRBus <= DATARATE_533MHZ)
		memcpy(&ddr_cfg_regs, &ddr_cfg_regs_533, sizeof(ddr_cfg_regs));
	else if(sysinfo.freqDDRBus <= DATARATE_667MHZ)
		memcpy(&ddr_cfg_regs, &ddr_cfg_regs_667, sizeof(ddr_cfg_regs));
	else if(sysinfo.freqDDRBus <= DATARATE_800MHZ)
		memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs));
	else
		panic("Unsupported DDR data rate %s MT/s data rate\n",
					strmhz(buf, sysinfo.freqDDRBus));

	cpu = gd->cpu;
	/* P1020 and it's derivatives support max 32bit DDR width */
	if(cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E ||
		cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) {
		ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE;
		ddr_cfg_regs.cs[0].bnds = 0x0000001F;
		ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
	}
	else
		ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;

	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);

	return ddr_size;
}
Beispiel #27
0
/*
 * Fixed sdram init -- doesn't use serial presence detect.
 */
phys_size_t fixed_sdram(void)
{
	int i;
	char buf[32];
	fsl_ddr_cfg_regs_t ddr_cfg_regs;
	phys_size_t ddr_size;
	ulong ddr_freq, ddr_freq_mhz;

	ddr_freq = get_ddr_freq(0);
	ddr_freq_mhz = ddr_freq / 1000000;

	printf("Configuring DDR for %s MT/s data rate\n",
				strmhz(buf, ddr_freq));

	for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
		if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
		   (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
			memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
							sizeof(ddr_cfg_regs));
			break;
		}
	}

	if (fixed_ddr_parm_0[i].max_freq == 0)
		panic("Unsupported DDR data rate %s MT/s data rate\n",
					strmhz(buf, ddr_freq));

	ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);

	if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
					LAW_TRGT_IF_DDR_1) < 0) {
		printf("ERROR setting Local Access Windows for DDR\n");
		return 0;
	}

	return ddr_size;
}
Beispiel #28
0
int print_cpuinfo(void)
{
	char buf[120], mhz[8];
	uint32_t id0, id1;

	asm volatile ("rsr %0, 176\n"
		      "rsr %1, 208\n"
		      : "=r"(id0), "=r"(id1));

	sprintf(buf, "CPU:   Xtensa %s (id: %08x:%08x) at %s MHz\n",
		XCHAL_CORE_ID, id0, id1, strmhz(mhz, gd->cpu_clk));
	puts(buf);
	return 0;
}
Beispiel #29
0
int checkboard(void)
{
/*
	char  revision = BOARD_REV;
*/
	ulong busfreq  = get_bus_freq(0);
	char  buf[32];

	puts ("CPC45  ");
/*
	printf("Revision %d ", revision);
*/
	printf("Local Bus at %s MHz\n", strmhz(buf, busfreq));

	return 0;
}
Beispiel #30
0
int print_cpuinfo(void)
{
	char buf[32];

	unsigned char resetsource = mbar_readLong(SIM_RSR);
	printf("CPU:   Freescale Coldfire MCF5253 at %s MHz\n",
	       strmhz(buf, CONFIG_SYS_CLK));

	if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
		printf("Reset:%s%s\n",
		       (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset"
		       : "",
		       (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" :
		       "");
	}
	return 0;
}