/* Get I/O permissions with automatic permission release on shutdown. */
int rget_io_perms(void)
{
#if IS_X86 && !(defined(__DJGPP__) || defined(__LIBPAYLOAD__))
#if defined (__sun)
if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0) {
#elif IS_BSD
if ((io_fd = open("/dev/io", O_RDWR)) < 0) {
#elif IS_LINUX || IS_MACOSX
if (iopl(3) != 0) {
#endif
msg_perr("ERROR: Could not get I/O privileges (%s).\n"
"You need to be root.\n", strerror(errno));
#if defined (__OpenBSD__)
msg_perr("Please set securelevel=-1 in /etc/rc.securelevel and reboot, or reboot into \n");
msg_perr("single user mode.\n");
#endif
return 1;
} else {
register_shutdown(release_io_perms, NULL);
}
#else
/* DJGPP and libpayload environments have full PCI port I/O permissions by default. */
/* PCI port I/O support is unimplemented on PPC/MIPS and unavailable on ARM. */
#endif
return 0;
}
void mmio_writeb(uint8_t val, void *addr)
{
*(volatile uint8_t *) addr = val;
sync_primitive();
}
void mmio_writew(uint16_t val, void *addr)
{
*(volatile uint16_t *) addr = val;
sync_primitive();
}
void get_io_perms(void)
{
#if defined(__DJGPP__) || defined(__LIBPAYLOAD__) || defined(__DOS__)
/* We have full permissions by default. */
return;
#else
#if defined (__sun) && (defined(__i386) || defined(__amd64))
if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0) {
#elif defined(__FreeBSD__) || defined (__DragonFly__)
if ((io_fd = open("/dev/io", O_RDWR)) < 0) {
#else
if (iopl(3) != 0) {
#endif
msg_perr("ERROR: Could not get I/O privileges (%s).\n"
"You need to be root.\n", strerror(errno));
#if defined (__OpenBSD__)
msg_perr("Please set securelevel=-1 in /etc/rc.securelevel "
"and reboot, or reboot into \n");
msg_perr("single user mode.\n");
#endif
exit(1);
}
#endif
}
void release_io_perms(void)
{
#if defined(__FreeBSD__) || defined(__DragonFly__)
close(io_fd);
#endif
}
#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
static inline void sync_primitive(void)
{
/* Prevent reordering and/or merging of reads/writes to hardware.
* Such reordering and/or merging would break device accesses which
* depend on the exact access order.
*/
asm("eieio" : : : "memory");
}
/* PCI port I/O is not yet implemented on PowerPC. */
void get_io_perms(void)
{
}
/* PCI port I/O is not yet implemented on PowerPC. */
void release_io_perms(void)
{
}
#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips)
/* sync primitive is not needed because /dev/mem on MIPS uses uncached accesses
* in mode 2 which has a strongly ordered memory model.
*/
static inline void sync_primitive(void)
{
}
/* PCI port I/O is not yet implemented on MIPS. */
void get_io_perms(void)
{
}
/* PCI port I/O is not yet implemented on MIPS. */
void release_io_perms(void)
{
}
#else
#error Unknown architecture
#endif
void mmio_writeb(uint8_t val, void *addr)
{
*(volatile uint8_t *) addr = val;
sync_primitive();
}
void mmio_writel(uint32_t val, void *addr)
{
*(volatile uint32_t *) addr = val;
sync_primitive();
}
