/**
* Configure Timer Counter 0 to generate an interrupt every 1s.
*/
static void configure_tc(void)
{
/*
* Aqui atualizamos o clock da cpu que foi configurado em sysclk init
*
* O valor atual está em : 120_000_000 Hz (120Mhz)
*/
uint32_t ul_sysclk = sysclk_get_cpu_hz();
/*
* Ativa o clock do periférico TC 0
*/
pmc_enable_periph_clk(ID_TC0);
// Configura TC para operar no modo de comparação e trigger RC
tc_init(TC0,0,TC_CMR_CPCTRG | TC_CMR_TCCLKS_TIMER_CLOCK5);
// Valor para o contador de um em um segundo.
tc_write_rc(TC0,0,32768);
NVIC_EnableIRQ((IRQn_Type) ID_TC0);
tc_enable_interrupt(TC0,0,TC_IER_CPCS);
tc_start(TC0, 0);
}
/**
* \internal
* \brief Initialize Proxy PLC controller.
*
* This function will change the system clock prescaler configuration to
* match the parameters.
*
* \note The parameters to this function are device-specific.
*
*/
static void _pplc_if_config(void)
{
uint32_t ul_cpuhz;
uint8_t uc_div;
ul_cpuhz = sysclk_get_cpu_hz();
uc_div = ul_cpuhz / gs_ul_pplc_clock;
/* Enable SPI peripheral. */
spi_enable_clock(PPLC_SPI_MODULE);
/* Reset SPI */
spi_disable(PPLC_SPI_MODULE);
spi_reset(PPLC_SPI_MODULE);
/* Configure SPI */
spi_set_master_mode(PPLC_SPI_MODULE);
spi_disable_mode_fault_detect(PPLC_SPI_MODULE);
spi_set_peripheral_chip_select_value(PPLC_SPI_MODULE, PPLC_PCS);
spi_set_clock_polarity(PPLC_SPI_MODULE, PPLC_CS, 0);
spi_set_clock_phase(PPLC_SPI_MODULE, PPLC_CS, 1);
spi_set_bits_per_transfer(PPLC_SPI_MODULE, PPLC_CS, SPI_CSR_BITS_8_BIT);
spi_set_fixed_peripheral_select(PPLC_SPI_MODULE);
spi_set_baudrate_div(PPLC_SPI_MODULE, PPLC_CS, uc_div);
spi_set_transfer_delay(PPLC_SPI_MODULE, PPLC_CS, PPLC_DLYBS,
PPLC_DLYBCT);
spi_configure_cs_behavior(PPLC_SPI_MODULE, PPLC_CS, SPI_CS_RISE_NO_TX);
/* Get board PPLC PDC base address and enable receiver and transmitter */
g_pplc_pdc = spi_get_pdc_base(PPLC_SPI_MODULE);
spi_enable(PPLC_SPI_MODULE);
}
/**
* \brief Test LIN transmit.
*
* This test initializes the LIN and start a transmit.
*
* \param test Current test case.
*/
static void run_lin_test(const struct test_case *test)
{
st_lin_message lin_desc;
/* Enable the peripheral clock in the PMC. */
pmc_enable_periph_clk(ID_USART0);
/* Enable LIN transceiver */
gpio_set_pin_high(PIN_USART0_CTS_IDX);
gpio_set_pin_high(PIN_USART0_RTS_IDX);
/* Node 0: LIN_MASTER_MODE */
lin_init(USART0, true, LIN_MASTER_NODE_NUM, 9600, sysclk_get_cpu_hz());
/* Configure lin_descriptor */
/* Init LIN data Node 0 */
/* Object 0 */
lin_desc.uc_id = LIN_FRAME_ID_12;
lin_desc.uc_dlc = sizeof(lin_data_node);
lin_desc.lin_cmd = PUBLISH;
lin_desc.uc_status = 0;
lin_desc.uc_pt_data = lin_data_node;
lin_register_descriptor(LIN_MASTER_NODE_NUM, 0, &lin_desc);
configure_tc();
/* In case of Master Mode, the timing transmission starts... */
tc_start(TC0, 0);
/* Configure and enable interrupt of USART */
NVIC_EnableIRQ(USART0_IRQn);
usart_enable_interrupt(USART0, US_IER_LINTC);
delay_ms(200);
test_assert_true(test, ul_LIN_int_flag, "LIN transmit failed!");
}
/**
* \brief initialize an I2C interface using given config
*
* \param[in] hal - opaque ptr to HAL data
* \param[in] cfg - interface configuration
*
* \return ATCA_STATUS
*/
ATCA_STATUS hal_i2c_init(void *hal, ATCAIfaceCfg *cfg)
{
// set to default i2c bus
if (cfg->atcai2c.bus > MAX_I2C_BUSES - 1)
cfg->atcai2c.bus = 0;
int bus = cfg->atcai2c.bus; // 0-based logical bus number
ATCAHAL_t *phal = (ATCAHAL_t*)hal;
if (i2c_bus_ref_ct == 0) // power up state, no i2c buses will have been used
for (int i = 0; i < MAX_I2C_BUSES; i++)
i2c_hal_data[i] = NULL;
i2c_bus_ref_ct++; // total across buses
if (bus >= 0 && bus < MAX_I2C_BUSES) {
// if this is the first time this bus and interface has been created, do the physical work of enabling it
if (i2c_hal_data[bus] == NULL) {
i2c_hal_data[bus] = malloc(sizeof(ATCAI2CMaster_t));
i2c_hal_data[bus]->ref_ct = 1; // buses are shared, this is the first instance
switch (bus) {
case 0:
i2c_hal_data[bus]->twi_id = ID_TWI0;
i2c_hal_data[bus]->twi_master_instance = TWI0;
break;
case 1:
i2c_hal_data[bus]->twi_id = ID_TWI1;
i2c_hal_data[bus]->twi_master_instance = TWI1;
// configure TWI1 pins
gpio_configure_pin(PIO_PB4_IDX, (PIO_PERIPH_A | PIO_PULLUP));
gpio_configure_pin(PIO_PB5_IDX, (PIO_PERIPH_A | PIO_PULLUP));
// disable JTAG
MATRIX->CCFG_SYSIO |= (1 << 4) | (1 << 5);
break;
}
pmc_enable_periph_clk(i2c_hal_data[bus]->twi_id);
opt_twi_master.master_clk = sysclk_get_cpu_hz();
opt_twi_master.speed = cfg->atcai2c.baud;
opt_twi_master.smbus = 0;
twi_master_init(i2c_hal_data[bus]->twi_master_instance, &opt_twi_master);
// store this for use during the release phase
i2c_hal_data[bus]->bus_index = bus;
}else {
// otherwise, another interface already initialized the bus, so this interface will share it and any different
// cfg parameters will be ignored...first one to initialize this sets the configuration
i2c_hal_data[bus]->ref_ct++;
}
phal->hal_data = i2c_hal_data[bus];
return ATCA_SUCCESS;
}
return ATCA_COMM_FAIL;
}
/**
* \brief Run unit tests for MT48LC16m16a2tg7 SDRAM
* \return 0 which should never occur.
*/
int main (void)
{
const usart_serial_options_t usart_serial_options = {
.baudrate = CONF_TEST_BAUDRATE,
.charlength = CONF_TEST_CHARLENGTH,
.paritytype = CONF_TEST_PARITY,
.stopbits = CONF_TEST_STOPBITS,
};
sysclk_init();
board_init();
stdio_serial_init(CONF_TEST_USART, &usart_serial_options);
sdramc_init(sysclk_get_cpu_hz());
// Define all the test cases
DEFINE_TEST_CASE(data_integrity_test, NULL, run_data_integrity_test,
NULL, "Data integrity test");
// Put test case addresses in an array
DEFINE_TEST_ARRAY(ebi_sdram_tests) = {
&data_integrity_test,
};
// Define the test suite
DEFINE_TEST_SUITE(ebi_sdram_suite, ebi_sdram_tests,
"UC3 EBI driver w/ SDRAM test suite");
// Set up the test data pointer and run all tests in the suite
test_set_data(¶ms);
test_suite_run(&ebi_sdram_suite);
while (true);
return (0);
}
static BaseType_t prvGMACInit( void )
{
uint32_t ncfgr;
gmac_options_t gmac_option;
memset( &gmac_option, '\0', sizeof( gmac_option ) );
gmac_option.uc_copy_all_frame = 0;
gmac_option.uc_no_boardcast = 0;
memcpy( gmac_option.uc_mac_addr, ucMACAddress, sizeof( gmac_option.uc_mac_addr ) );
gs_gmac_dev.p_hw = GMAC;
gmac_dev_init( GMAC, &gs_gmac_dev, &gmac_option );
NVIC_SetPriority( GMAC_IRQn, configMAC_INTERRUPT_PRIORITY );
NVIC_EnableIRQ( GMAC_IRQn );
/* Contact the Ethernet PHY and store it's address in 'ethernet_phy_addr' */
ethernet_phy_init( GMAC, ETHERNET_CONF_PHY_ADDR, sysclk_get_cpu_hz() );
ethernet_phy_auto_negotiate( GMAC, ethernet_phy_addr );
ethernet_phy_set_link( GMAC, ethernet_phy_addr, 1 );
/* The GMAC driver will call a hook prvRxCallback(), which
in turn will wake-up the task by calling vTaskNotifyGiveFromISR() */
gmac_dev_set_rx_callback( &gs_gmac_dev, prvRxCallback );
gmac_set_address( GMAC, 1, (uint8_t*)llmnr_mac_address );
ncfgr = GMAC_NCFGR_SPD | GMAC_NCFGR_FD;
GMAC->GMAC_NCFGR = ( GMAC->GMAC_NCFGR & ~( GMAC_NCFGR_SPD | GMAC_NCFGR_FD ) ) | ncfgr;
return 1;
}
/**
* \brief Configure to trigger AFEC by TIOA output of timer.
*/
static void configure_tc_trigger(void)
{
uint32_t ul_div = 0;
uint32_t ul_tc_clks = 0;
uint32_t ul_sysclk = sysclk_get_cpu_hz();
/* Enable peripheral clock. */
pmc_enable_periph_clk(ID_TC0);
/* TIOA configuration */
ioport_set_pin_mode(PIN_TC0_TIOA0, PIN_TC0_TIOA0_FLAGS);
ioport_disable_pin(PIN_TC0_TIOA0);
/* Configure TC for a 10Hz frequency and trigger on RC compare. */
tc_find_mck_divisor(10, ul_sysclk, &ul_div, &ul_tc_clks, ul_sysclk);
tc_init(TC0, 0, ul_tc_clks | TC_CMR_CPCTRG | TC_CMR_WAVE |
TC_CMR_ACPA_CLEAR | TC_CMR_ACPC_SET);
TC0->TC_CHANNEL[0].TC_RA = (ul_sysclk / ul_div) / 2;
TC0->TC_CHANNEL[0].TC_RC = (ul_sysclk / ul_div) / 1;
/* Start the Timer. */
tc_start(TC0, 0);
afec_set_trigger(AFEC0, AFEC_TRIG_TIO_CH_0);
}
/**
* \brief Configure USART in synchronous mode.
*
* \param ul_ismaster 1 for master, 0 for slave.
* \param ul_baudrate Baudrate for synchronous communication.
*
*/
static void configure_usart(uint32_t ul_ismaster, uint32_t ul_baudrate)
{
sam_usart_opt_t usart_console_settings = {
0,
US_MR_CHRL_8_BIT,
US_MR_PAR_NO,
US_MR_NBSTOP_1_BIT,
US_MR_CHMODE_NORMAL,
/* This field is only used in IrDA mode. */
0
};
usart_console_settings.baudrate = ul_baudrate;
/* Enable the peripheral clock in the PMC. */
sysclk_enable_peripheral_clock(BOARD_ID_USART);
/* Configure USART in SYNC. master or slave mode. */
if (ul_ismaster) {
usart_init_sync_master(BOARD_USART, &usart_console_settings, sysclk_get_cpu_hz());
} else {
usart_init_sync_slave(BOARD_USART, &usart_console_settings);
}
/* Disable all the interrupts. */
usart_disable_interrupt(BOARD_USART, ALL_INTERRUPT_MASK);
/* Enable TX & RX function. */
usart_enable_tx(BOARD_USART);
usart_enable_rx(BOARD_USART);
/* Configure and enable interrupt of USART. */
NVIC_EnableIRQ(USART_IRQn);
}
/************************************************************************
Configuration of the Pulse Width Modulation (PWM).
************************************************************************/
void PWMInit(void){
pmc_enable_periph_clk(ID_PWM);
pwm_channel_disable(PWM, PWM_CHANNEL_3);
pwm_channel_disable(PWM, PWM_CHANNEL_2);
pwm_clock_t clock_setting = {
.ul_clka = 50 * 19999,
.ul_clkb = 0,
.ul_mck = sysclk_get_cpu_hz()
};
pwm_init(PWM, &clock_setting);
InitPIN40();
InitPIN38();
}
/************************************************************************
Initiation of digital pin 40 on the Arduino Due board for PWM.
************************************************************************/
void InitPIN40(void)
{
PWMPin40.channel = PWM_CHANNEL_3;
PWMPin40.ul_prescaler = PWM_CMR_CPRE_CLKA;
PWMPin40.ul_duty = 0;
PWMPin40.ul_period = 19999;
pwm_channel_init(PWM, &PWMPin40);
pio_set_peripheral(PIOC, PIO_PERIPH_B, PIO_PC8B_PWML3);
pwm_channel_enable(PWM, PWM_CHANNEL_3);
}
/**
* \brief USART RS485 mode configuration.
*
* Configure USART in RS485 mode, asynchronous, 8 bits, 1 stop bit,
* no parity, 256000 bauds and enable its transmitter and receiver.
*/
void configure_usart(void)
{
const sam_usart_opt_t usart_console_settings = {
BOARD_USART_BAUDRATE,
US_MR_CHRL_8_BIT,
US_MR_PAR_NO,
US_MR_NBSTOP_1_BIT,
US_MR_CHMODE_NORMAL,
/* This field is only used in IrDA mode. */
0
};
/* Enable the peripheral clock in the PMC. */
sysclk_enable_peripheral_clock(BOARD_ID_USART);
/* Configure USART in RS485 mode. */
//jsi 7feb16 we want rs232 not rs485 for our application usart_init_rs485(BOARD_USART, &usart_console_settings,
//jsi 7feb16 we want rs232 not rs485 for our application sysclk_get_cpu_hz());
usart_init_rs232(BOARD_USART, &usart_console_settings, sysclk_get_cpu_hz());
/* enable transmitter timeguard, 4 bit period delay. */
usart_set_tx_timeguard(BOARD_USART, 4);
/* Disable all the interrupts. */
usart_disable_interrupt(BOARD_USART, ALL_INTERRUPT_MASK);
/* Enable TX & RX function. */
usart_enable_tx(BOARD_USART);
usart_enable_rx(BOARD_USART);
/* Configure and enable interrupt of USART. */
NVIC_EnableIRQ(USART_IRQn);
}
void config_uart(void){
/* configura pinos */
gpio_configure_group(PINS_UART0_PIO, PINS_UART0, PINS_UART0_FLAGS);
/* ativa clock */
sysclk_enable_peripheral_clock(CONSOLE_UART_ID);
/* Configuração UART */
const usart_serial_options_t uart_serial_options = {
.baudrate = CONF_UART_BAUDRATE,
.paritytype = UART_MR_PAR_NO,
.stopbits = 0
};
stdio_serial_init((Usart *)CONF_UART, &uart_serial_options);
}
static void configure_tc(void)
{
uint32_t ul_sysclk = sysclk_get_cpu_hz();
pmc_enable_periph_clk(ID_TC0);
tc_init(TC0, 0, TC_CMR_CPCTRG | TC_CMR_TCCLKS_TIMER_CLOCK5);
tc_write_rc(TC0, 0, 8192);
NVIC_EnableIRQ(ID_TC0);
tc_enable_interrupt(TC0, 0, TC_IER_CPCS);
tc_start(TC0,0);
}
/**
* \brief Low power application entry point.
*
* \return Unused (ANSI-C compatibility).
*/
int main(void)
{
/* Initialize the SAM system */
sysclk_init();
g_ul_current_mck = sysclk_get_cpu_hz();
board_init();
/* Initialize the console uart */
configure_console();
/* Output example information */
puts(STRING_HEADER);
/* Initialize the chip for the power consumption test */
init_chip();
/* Set default clock and re-configure UART */
set_default_working_clock();
reconfigure_console(g_ul_current_mck, CONF_UART_BAUDRATE);
/* Test core consumption */
test_core();
while (1) {
}
}
/**
* \brief Application entry point.
*
* \return Unused (ANSI-C compatibility).
*/
int main(void)
{
/* Initialize the SAM4 system */
stop_wdt();
sysclk_init();
board_init();
/* Set up SysTick Timer for 1 msec interrupts. */
if (SysTick_Config(sysclk_get_cpu_hz() / (uint32_t) 1000)) {
/* Capture error. */
while (1) {
}
}
/* Flash the LED. */
while (1) {
/* Turn on the LED. */
LED_On(LED0);
/* Delay 1000 Msec. */
delay_ms((uint32_t) 1000);
/* Turn off the LED. */
LED_Off(LED0);
/* Delay 1000 Msec. */
delay_ms((uint32_t) 1000);
}
}
int main(void)
{
/* Use static volatile to make it available in debug watch */
static volatile bool pin_val;
sysclk_init();
board_init();
ioport_init();
delay_init(sysclk_get_cpu_hz());
/* Set output direction on the given LED IOPORTs */
ioport_set_pin_dir(EXAMPLE_LED, IOPORT_DIR_OUTPUT);
/* Set direction and pullup on the given button IOPORT */
ioport_set_pin_dir(EXAMPLE_BUTTON, IOPORT_DIR_INPUT);
ioport_set_pin_mode(EXAMPLE_BUTTON, IOPORT_MODE_PULLUP);
/* Set LED IOPORTs high */
ioport_set_pin_level(EXAMPLE_LED, IOPORT_PIN_LEVEL_HIGH);
while (true) {
/* Toggle LED IOPORTs with half a second interval */
ioport_toggle_pin_level(EXAMPLE_LED);
delay_ms(500);
/* Get value from button port */
/* Use watch with debugger to see it */
pin_val = ioport_get_pin_level(EXAMPLE_BUTTON);
}
}
/**
* \brief Test Synchronous clock
*
* This test enables source clock for main clock, sets CPU/HSB,
* PBA,PBB,PBC(if have), PBD(if have) division factor, and then check
* if the chip is set correctly.
*
* \note It's not easy to measure CPU/HSB,PBA... frequency, even through
* some chips have freqm module. Using external module may cause some
* reliability issue. Since synchronous clocks share the common root
* main clock, they only need set division factor. So we just test
* the related registers if set correctly after calling common clock
* service.
*
* \param test Current test case.
*/
static void run_sync_clock_test(const struct test_case *test)
{
bool status;
/* avoid Cppcheck Warning */
UNUSED(status);
sysclk_init();
//PBA clock set, usart can be used
usart_ready = 1;
#ifdef CONFIG_CPU_HZ
status = (CONFIG_CPU_HZ == sysclk_get_cpu_hz());
test_assert_true(test, status, "CPU clock set fail");
#endif
#ifdef CONFIG_PBA_HZ
status = (CONFIG_PBA_HZ == sysclk_get_pba_hz());
test_assert_true(test, status, "PBA clock set fail");
#endif
#ifdef CONFIG_PBB_HZ
status = (CONFIG_PBB_HZ == sysclk_get_pbb_hz());
test_assert_true(test, status, "PBB clock set fail");
#endif
#ifdef CONFIG_PBC_HZ
status = (CONFIG_PBC_HZ == sysclk_get_pbc_hz());
test_assert_true(test, status, "PBC clock set fail");
#endif
#ifdef CONFIG_PBD_HZ
status = (CONFIG_PBD_HZ == sysclk_get_pbd_hz());
test_assert_true(test, status, "PBD clock set fail");
#endif
}
/**
* \brief Test flash configure functions.
*
* \note This test gets the default wait state first, and then it will
* initialize the flash again and set/adaptively set the wait state.
*
* \param test Current test case.
*/
static void run_flash_configure_test(const struct test_case *test)
{
uint32_t ul_default_ws;
uint32_t ul_tmp_ws;
uint32_t ul_mck = sysclk_get_cpu_hz();
/* Backup default wait state */
ul_default_ws = flash_get_wait_state(IFLASH_ADDR);
/* Check the flash init function */
flash_init(FLASH_ACCESS_MODE_128, 6);
/* Get the wait state set by flash_init */
ul_tmp_ws = flash_get_wait_state(IFLASH_ADDR);
/* Validate the flash initialization function */
test_assert_true(test, ul_tmp_ws == 6,
"Test flash configure: flash init error!");
/* Set the new wait state */
flash_set_wait_state(IFLASH_ADDR, ul_default_ws+1);
/* Get the wait state */
ul_tmp_ws = flash_get_wait_state(IFLASH_ADDR);
/* Validate the set flash wait state function */
test_assert_true(test, ul_tmp_ws == (ul_default_ws+1),
"Test flash configure: set wait state error!");
/* Adaptively set the wait state */
flash_set_wait_state_adaptively(IFLASH_ADDR);
/* Validate the adaptively set wait state function, get the wait state and
* check with the default>
*/
if (ul_mck < CHIP_FREQ_FWS_0) {
ul_tmp_ws = flash_get_wait_state(IFLASH_ADDR);
test_assert_true(test, ul_tmp_ws == 0,
"Test flash configure:adaptively set wait state error!");
} else if (ul_mck < CHIP_FREQ_FWS_1) {
ul_tmp_ws = flash_get_wait_state(IFLASH_ADDR);
test_assert_true(test, ul_tmp_ws == 1,
"Test flash configure:adaptively set wait state error!");
} else if (ul_mck < CHIP_FREQ_FWS_2) {
ul_tmp_ws = flash_get_wait_state(IFLASH_ADDR);
test_assert_true(test, ul_tmp_ws == 2,
"Test flash configure:adaptively set wait state error!");
#if (SAM3XA || SAM3U)
} else if (ul_mck < CHIP_FREQ_FWS_3) {
ul_tmp_ws = flash_get_wait_state(IFLASH_ADDR);
test_assert_true(test, ul_tmp_ws == 3,
"Test flash configure:adaptively set wait state error!");
} else {
ul_tmp_ws = flash_get_wait_state(IFLASH_ADDR);
test_assert_true(test, ul_tmp_ws == 4,
"Test flash configure:adaptively set wait state error!");
}
#elif (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CP || SAM4CM || \
SAMV71 || SAMV70 || SAMS70 || SAME70)
} else if (ul_mck < CHIP_FREQ_FWS_3) {
/**
* \brief Set the specified SPI clock configuration.
*
* \param configuration Index of the configuration to set.
*/
static void spi_set_clock_configuration(uint8_t configuration)
{
gs_ul_spi_clock = gs_ul_clock_configurations[configuration];
printf("Setting SPI clock #%lu ... \n\r", (unsigned long)gs_ul_spi_clock);
spi_set_baudrate_div(SPI_MASTER_BASE, SPI_CHIP_SEL,
(sysclk_get_cpu_hz() / gs_ul_spi_clock));
}
/**
* \brief Configure to trigger ADC by TIOA output of timer.
*/
static void configure_time_trigger(void)
{
uint32_t ul_div = 0;
uint32_t ul_tc_clks = 0;
uint32_t ul_sysclk = sysclk_get_cpu_hz();
/* Enable peripheral clock. */
pmc_enable_periph_clk(ID_TC0);
/* TIOA configuration */
gpio_configure_pin(PIN_TC0_TIOA0, PIN_TC0_TIOA0_FLAGS);
/* Configure TC for a 1Hz frequency and trigger on RC compare. */
tc_find_mck_divisor(1, ul_sysclk, &ul_div, &ul_tc_clks, ul_sysclk);
tc_init(TC0, 0, ul_tc_clks | TC_CMR_CPCTRG | TC_CMR_WAVE |
TC_CMR_ACPA_CLEAR | TC_CMR_ACPC_SET);
TC0->TC_CHANNEL[0].TC_RA = (ul_sysclk / ul_div) / 2;
TC0->TC_CHANNEL[0].TC_RC = (ul_sysclk / ul_div) / 1;
/* Start the Timer. */
tc_start(TC0, 0);
/* Set TIOA0 trigger. */
#if SAM3S || SAM3N || SAM3XA || SAM4S || SAM4C
adc_configure_trigger(ADC, ADC_TRIG_TIO_CH_0, 0);
#elif SAM3U
#ifdef ADC_12B
adc12b_configure_trigger(ADC12B, ADC12B_TRIG_TIO_CH_0);
#else
adc_configure_trigger(ADC, ADC_TRIG_TIO_CH_0);
#endif
#endif
}
static void init_timer_isr(void)
{
if (SysTick_Config((sysclk_get_cpu_hz() / 1000) *
qt_measurement_period_msec)) {
printf("-F- Systick configuration error\n\r");
}
}
/**
* \brief USART RS485 mode configuration.
*
* Configure USART in RS485 mode, asynchronous, 8 bits, 1 stop bit,
* no parity, 256000 bauds and enable its transmitter and receiver.
*/
static void configure_usart(void)
{
const sam_usart_opt_t usart_console_settings = {
BOARD_USART_BAUDRATE,
US_MR_CHRL_8_BIT,
US_MR_PAR_NO,
US_MR_NBSTOP_1_BIT,
US_MR_CHMODE_NORMAL,
/* This field is only used in IrDA mode. */
0
};
/* Enable the peripheral clock in the PMC. */
sysclk_enable_peripheral_clock(BOARD_ID_USART);
/* Configure USART in RS485 mode. */
usart_init_rs485(BOARD_USART, &usart_console_settings,
sysclk_get_cpu_hz());
/* Disable all the interrupts. */
usart_disable_interrupt(BOARD_USART, ALL_INTERRUPT_MASK);
/* Enable TX & RX function. */
usart_enable_tx(BOARD_USART);
usart_enable_rx(BOARD_USART);
/* Configure and enable interrupt of USART. */
NVIC_EnableIRQ(USART_IRQn);
}
void sysclk_init(void)
{
/* Set up system clock dividers if different from defaults */
if ((CONFIG_SYSCLK_CPU_DIV > 0) || (CONFIG_SYSCLK_PBA_DIV > 0) ||
(CONFIG_SYSCLK_PBB_DIV > 0)) {
sysclk_set_prescalers(CONFIG_SYSCLK_CPU_DIV,
CONFIG_SYSCLK_PBA_DIV,
CONFIG_SYSCLK_PBB_DIV);
}
/* Switch to system clock selected by user */
switch (CONFIG_SYSCLK_SOURCE) {
case SYSCLK_SRC_RCSYS:
/* Already running from RCOSC */
break;
#ifdef BOARD_OSC0_HZ
case SYSCLK_SRC_OSC0:
osc_enable(OSC_ID_OSC0);
osc_wait_ready(OSC_ID_OSC0);
// Set a flash wait state depending on the new cpu frequency.
flash_set_bus_freq(BOARD_OSC0_HZ);
sysclk_set_source(SYSCLK_SRC_OSC0);
break;
#endif
#ifdef CONFIG_PLL0_SOURCE
case SYSCLK_SRC_PLL0: {
pll_enable_config_defaults(0);
// Set a flash wait state depending on the new cpu frequency.
flash_set_bus_freq(sysclk_get_cpu_hz());
sysclk_set_source(SYSCLK_SRC_PLL0);
break;
}
#endif
default:
Assert(false);
break;
}
/* If the user has specified clock masks, enable only requested clocks */
#if defined(CONFIG_SYSCLK_INIT_CPUMASK)
AVR32_PM.cpumask = SYSCLK_INIT_MINIMAL_CPUMASK | CONFIG_SYSCLK_INIT_CPUMASK;
#endif
#if defined(CONFIG_SYSCLK_INIT_PBAMASK)
AVR32_PM.pbamask = SYSCLK_INIT_MINIMAL_PBAMASK | CONFIG_SYSCLK_INIT_PBAMASK;
#endif
#if defined(CONFIG_SYSCLK_INIT_PBBMASK)
AVR32_PM.pbbmask = SYSCLK_INIT_MINIMAL_PBBMASK | CONFIG_SYSCLK_INIT_PBBMASK;
#endif
#if defined(CONFIG_SYSCLK_INIT_HSBMASK)
AVR32_PM.hsbmask = SYSCLK_INIT_MINIMAL_HSBMASK | CONFIG_SYSCLK_INIT_HSBMASK;
#endif
#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)
/* Signal that the internal frequencies are setup */
sysclk_initialized = true;
#endif
}
// [main_tc_configure]
static void configure_tc(void)
{
uint32_t ul_div;
uint32_t ul_tcclks;
uint32_t ul_sysclk = sysclk_get_cpu_hz();
/* Configure PMC */
pmc_enable_periph_clk(ID_TC0);
#if SAMG55
/* Enable PCK output */
pmc_disable_pck(PMC_PCK_3);
pmc_switch_pck_to_sclk(PMC_PCK_3, PMC_PCK_PRES_CLK_1);
pmc_enable_pck(PMC_PCK_3);
#endif
/** Configure TC for a 4Hz frequency and trigger on RC compare. */
tc_find_mck_divisor(4, ul_sysclk, &ul_div, &ul_tcclks, ul_sysclk);
tc_init(TC0, 0, ul_tcclks | TC_CMR_CPCTRG);
tc_write_rc(TC0, 0, (ul_sysclk / ul_div) / 4);
/* Configure and enable interrupt on RC compare */
NVIC_EnableIRQ((IRQn_Type) ID_TC0);
tc_enable_interrupt(TC0, 0, TC_IER_CPCS);
#ifdef LED1_GPIO
/** Start the counter if LED1 is enabled. */
if (g_b_led1_active) {
tc_start(TC0, 0);
}
#else
tc_start(TC0, 0);
#endif
}
/*! \brief Initializes SD/MMC resources: GPIO, MCI and SD/MMC.
*/
static void sd_mmc_mci_resources_init(void)
{
static const gpio_map_t SD_MMC_MCI_GPIO_MAP = {
{SD_SLOT_8BITS_CLK_PIN, SD_SLOT_8BITS_CLK_FUNCTION}, // SD CLK.
{SD_SLOT_8BITS_CMD_PIN, SD_SLOT_8BITS_CMD_FUNCTION}, // SD CMD.
{SD_SLOT_8BITS_DATA0_PIN, SD_SLOT_8BITS_DATA0_FUNCTION}, // SD DAT[0].
{SD_SLOT_8BITS_DATA1_PIN, SD_SLOT_8BITS_DATA1_FUNCTION}, // DATA Pin.
{SD_SLOT_8BITS_DATA2_PIN, SD_SLOT_8BITS_DATA2_FUNCTION}, // DATA Pin.
{SD_SLOT_8BITS_DATA3_PIN, SD_SLOT_8BITS_DATA3_FUNCTION}, // DATA Pin.
{SD_SLOT_8BITS_DATA4_PIN, SD_SLOT_8BITS_DATA4_FUNCTION}, // DATA Pin.
{SD_SLOT_8BITS_DATA5_PIN, SD_SLOT_8BITS_DATA5_FUNCTION}, // DATA Pin.
{SD_SLOT_8BITS_DATA6_PIN, SD_SLOT_8BITS_DATA6_FUNCTION}, // DATA Pin.
{SD_SLOT_8BITS_DATA7_PIN, SD_SLOT_8BITS_DATA7_FUNCTION} // DATA Pin.
};
// MCI options.
static const mci_options_t MCI_OPTIONS = {
.card_speed = 400000,
.card_slot = SD_SLOT_8BITS, // Default card initialization.
};
// Assign I/Os to MCI.
gpio_enable_module(SD_MMC_MCI_GPIO_MAP,
sizeof(SD_MMC_MCI_GPIO_MAP) /
sizeof(SD_MMC_MCI_GPIO_MAP[0]));
// Enable pull-up for Card Detect.
gpio_enable_pin_pull_up(SD_SLOT_8BITS_CARD_DETECT);
// Enable pull-up for Write Protect.
gpio_enable_pin_pull_up(SD_SLOT_8BITS_WRITE_PROTECT);
sd_mmc_mci_init(&MCI_OPTIONS, sysclk_get_pbb_hz(), sysclk_get_cpu_hz());
}
int main (void)
{
/* Insert system clock initialization code here (sysclk_init()). */
board_init();
sysclk_init();
delay_init(sysclk_get_cpu_hz());
//gpio_configure_pin(PORTA5,1);
ioport_init();
ioport_set_pin_dir(LED_GREEN,IOPORT_DIR_OUTPUT);
ioport_set_pin_dir(LED_RED,IOPORT_DIR_OUTPUT);
/* Insert application code here, after the board has been initialized. */
ioport_set_pin_high(LED_RED);
ioport_set_pin_low(LED_GREEN);
//gpio_set_pin_high(PORTA5);
while(true){
ioport_toggle_pin(LED_GREEN);
ioport_toggle_pin(LED_RED);
delay_ms(500);
}
}
/**
* \brief Test SDRAMC initialize interface, through SDRAMC read/write access.
*
* \param test Current test case.
*/
static void run_sdramc_test(const struct test_case *test)
{
uint32_t ul;
uint32_t *pul = (uint32_t *)BOARD_SDRAM_ADDR;
/* Enable SMC peripheral clock */
pmc_enable_periph_clk(ID_SMC);
/* Complete SDRAM configuration */
sdramc_init((sdramc_memory_dev_t *)&SDRAM_MICRON_MT48LC16M16A2,
sysclk_get_cpu_hz());
for (ul = 0; ul < SDRAMC_ADDR_LINE_LENGTH; ++ul) {
pul[1 << ul] = SDRAMC_UNIT_TEST_CONST_WRITE_DATA;
}
for (ul = 0; ul < SDRAMC_ADDR_LINE_LENGTH; ++ul) {
test_assert_true(test,
pul[1 << ul] == SDRAMC_UNIT_TEST_CONST_WRITE_DATA,
"SDRAMC write test failed");
}
for (ul = 0; ul < SDRAMC_ADDR_LINE_LENGTH; ++ul) {
pul[1 << ul] = SDRAMC_UNIT_TEST_CONST_READ_DATA;
}
for (ul = 0; ul < SDRAMC_ADDR_LINE_LENGTH; ++ul) {
test_assert_true(test,
pul[1 << ul] == SDRAMC_UNIT_TEST_CONST_READ_DATA,
"SDRAMC read test failed");
}
}
void uart_config(uint8_t port, usb_cdc_line_coding_t * cfg)
{
uint8_t reg_ctrlc;
uint16_t bsel;
reg_ctrlc = USART_CMODE_ASYNCHRONOUS_gc;
switch(cfg->bCharFormat)
{
case CDC_STOP_BITS_2:
reg_ctrlc |= USART_SBMODE_bm;
break;
case CDC_STOP_BITS_1:
default:
// Default stop bit = 1 stop bit
break;
}
switch(cfg->bParityType)
{
case CDC_PAR_EVEN:
reg_ctrlc |= USART_PMODE_EVEN_gc;
break;
case CDC_PAR_ODD:
reg_ctrlc |= USART_PMODE_ODD_gc;
break;
default:
case CDC_PAR_NONE:
reg_ctrlc |= USART_PMODE_DISABLED_gc;
break;
}
switch(cfg->bDataBits)
{
case 5:
reg_ctrlc |= USART_CHSIZE_5BIT_gc;
break;
case 6:
reg_ctrlc |= USART_CHSIZE_6BIT_gc;
break;
case 7:
reg_ctrlc |= USART_CHSIZE_7BIT_gc;
break;
default:
case 8:
reg_ctrlc |= USART_CHSIZE_8BIT_gc;
break;
case 9:
reg_ctrlc |= USART_CHSIZE_9BIT_gc;
break;
}
sysclk_enable_module(USART_PORT_SYSCLK, USART_SYSCLK);
// Set configuration
USART.CTRLC = reg_ctrlc;
// Update baudrate
//usart_set_baudrate(&USART, cfg->dwDTERate, sysclk_get_cpu_hz());
usart_set_baudrate(&USART, 115200, sysclk_get_cpu_hz());
}
BaseType_t xNetworkInterfaceInitialise( void )
{
gmac_options_t xGMACOptions;
extern uint8_t ucMACAddress[ 6 ];
const TickType_t xPHYDelay_400ms = 400UL;
BaseType_t xReturn = pdFALSE;
/* Ensure PHY is ready. */
vTaskDelay( xPHYDelay_400ms / portTICK_RATE_MS );
/* Enable GMAC clock. */
pmc_enable_periph_clk( ID_GMAC );
/* Fill in GMAC options */
xGMACOptions.uc_copy_all_frame = 0;
xGMACOptions.uc_no_boardcast = 0;
memcpy( xGMACOptions.uc_mac_addr, ucMACAddress, sizeof( ucMACAddress ) );
xGMACStruct.p_hw = GMAC;
/* Init GMAC driver structure. */
gmac_dev_init( GMAC, &xGMACStruct, &xGMACOptions );
/* Init MAC PHY driver. */
if( ethernet_phy_init( GMAC, BOARD_GMAC_PHY_ADDR, sysclk_get_cpu_hz() ) == GMAC_OK )
{
/* Auto Negotiate, work in RMII mode. */
if( ethernet_phy_auto_negotiate( GMAC, BOARD_GMAC_PHY_ADDR ) == GMAC_OK )
{
/* Establish Ethernet link. */
vTaskDelay( xPHYDelay_400ms * 2UL );
if( ethernet_phy_set_link( GMAC, BOARD_GMAC_PHY_ADDR, 1 ) == GMAC_OK )
{
/* Register the callbacks. */
gmac_dev_set_rx_callback( &xGMACStruct, prvGMACRxCallback );
/* The Rx deferred interrupt handler task is created at the
highest possible priority to ensure the interrupt handler can
return directly to it no matter which task was running when the
interrupt occurred. */
xTaskCreate( prvGMACDeferredInterruptHandlerTask,/* The function that implements the task. */
"MACTsk",
configMINIMAL_STACK_SIZE, /* Stack allocated to the task (defined in words, not bytes). */
NULL, /* The task parameter is not used. */
configMAX_PRIORITIES - 1, /* The priority assigned to the task. */
&xMACEventHandlingTask ); /* The handle is stored so the ISR knows which task to notify. */
/* Enable the interrupt and set its priority as configured.
THIS DRIVER REQUIRES configMAC_INTERRUPT_PRIORITY TO BE DEFINED,
PREFERABLY IN FreeRTOSConfig.h. */
NVIC_SetPriority( GMAC_IRQn, configMAC_INTERRUPT_PRIORITY );
NVIC_EnableIRQ( GMAC_IRQn );
xReturn = pdPASS;
}
}
}
return xReturn;
}
/** Initialize the SPI peripheral
*
* Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
* @param[out] obj The SPI object to initialize
* @param[in] mosi The pin to use for MOSI
* @param[in] miso The pin to use for MISO
* @param[in] sclk The pin to use for SCLK
*/
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk)
{
MBED_ASSERT(obj);
MBED_ASSERT(mosi !=NC && miso!=NC && sclk !=NC );
if (g_sys_init == 0) {
sysclk_init();
system_board_init();
g_sys_init = 1;
}
Spi *sercombase = pinmap_find_sercom(mosi,miso,sclk);
MBED_ASSERT(sercombase!=NC);
pinmap_find_spi_info(sercombase, obj);
MBED_ASSERT(obj->spi.flexcom!=NC);
MBED_ASSERT(obj->spi.pdc!=NC);
/* Configure SPI pins */
pin_function(mosi, pinmap_find_function(mosi, PinMap_SPI_MOSI));
ioport_disable_pin(mosi);
pin_function(miso, pinmap_find_function(miso, PinMap_SPI_MISO));
ioport_disable_pin(miso);
pin_function(sclk, pinmap_find_function(sclk, PinMap_SPI_SCLK));
ioport_disable_pin(sclk);
#if (SAMG55)
/* Enable the peripheral and set SPI mode. */
flexcom_enable(obj->spi.flexcom);
flexcom_set_opmode(obj->spi.flexcom, FLEXCOM_SPI);
#else
/* Configure an SPI peripheral. */
spi_enable_clock(sercombase);
#endif
spi_disable(sercombase);
spi_reset(sercombase);
spi_set_lastxfer(sercombase);
spi_set_master_mode(sercombase);
spi_disable_mode_fault_detect(sercombase);
spi_set_peripheral_chip_select_value(sercombase, SPI_CHIP_SEL);
spi_set_clock_polarity(sercombase, SPI_CHIP_SEL, SPI_CLK_POLARITY);
spi_set_clock_phase(sercombase, SPI_CHIP_SEL, SPI_CLK_PHASE);
spi_set_bits_per_transfer(sercombase, SPI_CHIP_SEL, SPI_CSR_BITS_8_BIT);
spi_set_baudrate_div(sercombase, SPI_CHIP_SEL,(sysclk_get_cpu_hz() / gSPI_clock));
spi_set_transfer_delay(sercombase, SPI_CHIP_SEL, SPI_DLYBS,SPI_DLYBCT);
spi_enable(sercombase);
pdc_disable_transfer(obj->spi.pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS);
obj->spi.spi_base=sercombase;
obj->spi.cs= SPI_CHIP_SEL;
obj->spi.polarity=SPI_CLK_POLARITY;
obj->spi.phase=SPI_CLK_PHASE;
obj->spi.transferrate=SPI_CSR_BITS_8_BIT;
obj->spi.is_slave=0;
}
void time_tick_init(void)
{
g_ms_ticks = 0;
/* Configure systick */
if (SysTick_Config(sysclk_get_cpu_hz() / TICK_US)) {
Assert(false);
}
}
void i2c400_init(void)
{
m_options.speed_reg = TWI_BAUD(sysclk_get_cpu_hz(),m_options.speed);
sysclk_enable_peripheral_clock(&TWI_I2C400);
twi_master_init(&TWI_I2C400,&m_options);
}
