static void check_reset_cause(void) { uint32_t status = MEC1322_VBAT_STS; uint32_t flags = 0; uint32_t rst_sts = MEC1322_PCR_CHIP_PWR_RST & (MEC1322_PWR_RST_STS_VCC1 | MEC1322_PWR_RST_STS_VBAT); /* Clear the reset causes now that we've read them */ MEC1322_VBAT_STS |= status; MEC1322_PCR_CHIP_PWR_RST |= rst_sts; /* * BIT[6] determine VCC1 reset */ if (rst_sts & MEC1322_PWR_RST_STS_VCC1) flags |= RESET_FLAG_RESET_PIN; flags |= MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS); MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS) = 0; if ((status & MEC1322_VBAT_STS_WDT) && !(flags & (RESET_FLAG_SOFT | RESET_FLAG_HARD | RESET_FLAG_HIBERNATE))) flags |= RESET_FLAG_WATCHDOG; system_set_reset_flags(flags); }
static void check_reset_cause(void) { uint32_t flags = 0; uint32_t raw_cause = NRF51_POWER_RESETREAS; if (raw_cause & 0x00000001) flags |= RESET_FLAG_RESET_PIN; if (raw_cause & 0x00000002) flags |= RESET_FLAG_WATCHDOG; /* * According to the data sheet, this bit is set by AIRCR.SYSRESETREQ. * However, th reset from J-Link also sets this bit. This could mislead * us. */ if (raw_cause & 0x00000004) flags |= RESET_FLAG_SOFT; if (raw_cause & 0x00070008) flags |= RESET_FLAG_OTHER; system_set_reset_flags(flags); /* clear it by writing 1's */ NRF51_POWER_RESETREAS = raw_cause; }
void test_init(void) { uint32_t state = system_get_scratchpad(); if (state & TEST_STATE_MASK(TEST_STATE_STEP_2)) { /* Power-F3-ESC */ system_set_reset_flags(system_get_reset_flags() | RESET_FLAG_RESET_PIN); mock_key(1, 1, 1); } else if (state & TEST_STATE_MASK(TEST_STATE_STEP_3)) { /* Power-F3-Down */ system_set_reset_flags(system_get_reset_flags() | RESET_FLAG_RESET_PIN); mock_key(6, 11, 1); } }
void system_pre_init(void) { timestamp_t t; if (load_time(&t)) force_time(t); ramdata_get_persistent(); __running_copy = get_image_copy(); if (__running_copy == SYSTEM_IMAGE_UNKNOWN) { __running_copy = SYSTEM_IMAGE_RO; system_set_reset_flags(load_reset_flags()); } *(uintptr_t *)(__host_flash + CONFIG_RO_MEM_OFF + 4) = (uintptr_t)__ro_jump_resetvec; *(uintptr_t *)(__host_flash + CONFIG_RW_MEM_OFF + 4) = (uintptr_t)__rw_jump_resetvec; }
static void check_reset_cause(void) { uint32_t status = MEC1322_VBAT_STS; uint32_t flags = 0; /* Clear the reset causes now that we've read them */ MEC1322_VBAT_STS |= status; if (status & (1 << 7) || check_vcc1_por()) flags |= RESET_FLAG_POWER_ON; flags |= MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS); MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS) = 0; if (status & (1 << 5) && !(flags & (RESET_FLAG_SOFT | RESET_FLAG_HARD | RESET_FLAG_HIBERNATE))) flags |= RESET_FLAG_WATCHDOG; system_set_reset_flags(flags); }
static void check_reset_cause(void) { uint32_t hib_status = LM4_HIBERNATE_HIBRIS; uint32_t raw_reset_cause = LM4_SYSTEM_RESC; uint32_t hib_wake_flags = hibdata_read(HIBDATA_INDEX_WAKE); uint32_t flags = 0; /* Clear the reset causes now that we've read them */ LM4_SYSTEM_RESC = 0; wait_for_hibctl_wc(); LM4_HIBERNATE_HIBIC = hib_status; hibdata_write(HIBDATA_INDEX_WAKE, 0); if (raw_reset_cause & 0x02) { /* * Full power-on reset of chip. This resets the flash * protection registers to their permanently-stored values. * Note that this is also triggered by hibernation, because * that de-powers the chip. */ flags |= RESET_FLAG_POWER_ON; } else if (!flags && (raw_reset_cause & 0x01)) { /* * LM4 signals the reset pin in RESC for all power-on resets, * even though the external pin wasn't asserted. Make setting * this flag mutually-exclusive with power on flag, so we can * use it to indicate a keyboard-triggered reset. */ flags |= RESET_FLAG_RESET_PIN; } if (raw_reset_cause & 0x04) flags |= RESET_FLAG_BROWNOUT; if (raw_reset_cause & 0x10) flags |= RESET_FLAG_SOFT; if (raw_reset_cause & 0x28) { /* Watchdog timer 0 or 1 */ flags |= RESET_FLAG_WATCHDOG; } /* Handle other raw reset causes */ if (raw_reset_cause && !flags) flags |= RESET_FLAG_OTHER; if ((hib_status & 0x09) && (hib_wake_flags & HIBDATA_WAKE_HARD_RESET)) { /* Hibernation caused by software-triggered hard reset */ flags |= RESET_FLAG_HARD; /* Consume the hibernate reasons so we don't see them below */ hib_status &= ~0x09; } if ((hib_status & 0x01) && (hib_wake_flags & HIBDATA_WAKE_RTC)) flags |= RESET_FLAG_RTC_ALARM; if ((hib_status & 0x08) && (hib_wake_flags & HIBDATA_WAKE_PIN)) flags |= RESET_FLAG_WAKE_PIN; if (hib_status & 0x04) flags |= RESET_FLAG_LOW_BATTERY; /* Restore then clear saved reset flags */ flags |= hibdata_read(HIBDATA_INDEX_SAVED_RESET_FLAGS); hibdata_write(HIBDATA_INDEX_SAVED_RESET_FLAGS, 0); system_set_reset_flags(flags); }