bool stm32f1_probe(struct target_s *target)
{
target->idcode = adiv5_ap_mem_read(adiv5_target_ap(target), DBGMCU_IDCODE) & 0xfff;
switch(target->idcode) {
case 0x410: /* Medium density */
case 0x412: /* Low denisty */
case 0x420: /* Value Line, Low-/Medium density */
target->driver = stm32f1_driver_str;
target->xml_mem_map = stm32f1_xml_memory_map;
target->flash_erase = stm32md_flash_erase;
target->flash_write = stm32f1_flash_write;
target_add_commands(target, stm32f1_cmd_list, "STM32 LD/MD");
return true;
case 0x414: /* High density */
case 0x418: /* Connectivity Line */
case 0x428: /* Value Line, High Density */
target->driver = stm32hd_driver_str;
target->xml_mem_map = stm32hd_xml_memory_map;
target->flash_erase = stm32hd_flash_erase;
target->flash_write = stm32f1_flash_write;
target_add_commands(target, stm32f1_cmd_list, "STM32 HD/CL");
return true;
case 0x422: /* STM32F30x */
case 0x432: /* STM32F37x */
target->driver = stm32f3_driver_str;
target->xml_mem_map = stm32hd_xml_memory_map;
target->flash_erase = stm32hd_flash_erase;
target->flash_write = stm32f1_flash_write;
target_add_commands(target, stm32f1_cmd_list, "STM32F3");
return true;
}
target->idcode = adiv5_ap_mem_read(adiv5_target_ap(target), DBGMCU_IDCODE_F0) & 0xfff;
switch(target->idcode) {
case 0x444: /* STM32F03 */
case 0x440: /* STM32F05 */
case 0x448: /* STM32F07 */
switch(target->idcode) {
case 0x444: /* STM32F03 */
target->driver = stm32f03_driver_str;
break;
case 0x440: /* STM32F05 */
target->driver = stm32f05_driver_str;
break;
case 0x448: /* STM32F07 */
target->driver = stm32f07_driver_str;
break;
}
target->xml_mem_map = stm32f1_xml_memory_map;
target->flash_erase = stm32md_flash_erase;
target->flash_write = stm32f1_flash_write;
target_add_commands(target, stm32f1_cmd_list, "STM32F0");
return true;
}
return false;
}
bool stm32f4_probe(target *t)
{
bool f2 = false;
uint32_t idcode;
idcode = target_mem_read32(t, DBGMCU_IDCODE);
idcode &= 0xFFF;
if (idcode == 0x411)
{
/* F405 revision A have a wrong IDCODE, use ARM_CPUID to make the
* distinction with F205. Revision is also wrong (0x2000 instead
* of 0x1000). See F40x/F41x errata. */
uint32_t cpuid = target_mem_read32(t, ARM_CPUID);
if ((cpuid & 0xFFF0) == 0xC240)
idcode = 0x413;
else
f2 = true;
}
switch(idcode) {
case 0x419: /* 427/437 */
/* Second bank for 2M parts. */
stm32f4_add_flash(t, 0x8100000, 0x10000, 0x4000, 12);
stm32f4_add_flash(t, 0x8110000, 0x10000, 0x10000, 16);
stm32f4_add_flash(t, 0x8120000, 0xE0000, 0x20000, 17);
/* Fall through for stuff common to F40x/F41x */
case 0x411: /* F205 */
case 0x413: /* F405 */
case 0x421: /* F446 */
case 0x423: /* F401 B/C RM0368 Rev.3 */
case 0x431: /* F411 RM0383 Rev.4 */
case 0x433: /* F401 D/E RM0368 Rev.3 */
t->driver = f2 ? stm32f2_driver_str : stm32f4_driver_str;
if (!f2)
target_add_ram(t, 0x10000000, 0x10000);
target_add_ram(t, 0x20000000, 0x30000);
stm32f4_add_flash(t, 0x8000000, 0x10000, 0x4000, 0);
stm32f4_add_flash(t, 0x8010000, 0x10000, 0x10000, 4);
stm32f4_add_flash(t, 0x8020000, 0xE0000, 0x20000, 5);
target_add_commands(t, stm32f4_cmd_list, f2 ? "STM32F2" :
"STM32F4");
break;
case 0x449: /* F7x6 RM0385 Rev.2 */
t->driver = stm32f7_driver_str;
target_add_ram(t, 0x00000000, 0x4000);
target_add_ram(t, 0x20000000, 0x50000);
stm32f4_add_flash(t, 0x8000000, 0x20000, 0x8000, 0);
stm32f4_add_flash(t, 0x8020000, 0x20000, 0x20000, 4);
stm32f4_add_flash(t, 0x8040000, 0xC0000, 0x40000, 5);
target_add_commands(t, stm32f4_cmd_list, "STM32F7");
break;
default:
return false;
}
t->idcode = idcode;
return true;
}
bool stm32f4_probe(target *t)
{
uint32_t idcode;
idcode = target_mem_read32(t, DBGMCU_IDCODE);
switch(idcode & 0xFFF) {
case 0x419: /* 427/437 */
/* Second bank for 2M parts. */
stm32f4_add_flash(t, 0x8100000, 0x10000, 0x4000, 12);
stm32f4_add_flash(t, 0x8110000, 0x10000, 0x10000, 16);
stm32f4_add_flash(t, 0x8120000, 0xE0000, 0x20000, 17);
/* Fall through for stuff common to F40x/F41x */
case 0x411: /* Documented to be 0x413! This is what I read... */
case 0x413: /* F407VGT6 */
case 0x423: /* F401 B/C RM0368 Rev.3 */
case 0x431: /* F411 RM0383 Rev.4 */
case 0x433: /* F401 D/E RM0368 Rev.3 */
t->driver = stm32f4_driver_str;
target_add_ram(t, 0x10000000, 0x10000);
target_add_ram(t, 0x20000000, 0x30000);
stm32f4_add_flash(t, 0x8000000, 0x10000, 0x4000, 0);
stm32f4_add_flash(t, 0x8010000, 0x10000, 0x10000, 4);
stm32f4_add_flash(t, 0x8020000, 0xE0000, 0x20000, 5);
target_add_commands(t, stm32f4_cmd_list, "STM32F4");
return true;
}
return false;
}
void kinetis_mdm_probe(ADIv5_AP_t *ap)
{
switch(ap->idr) {
case KINETIS_MDM_IDR_KZ03:
case KINETIS_MDM_IDR_K22F:
break;
default:
return;
}
target *t = target_new();
adiv5_ap_ref(ap);
t->priv = ap;
t->priv_free = (void*)adiv5_ap_unref;
t->driver = "Kinetis Recovery (MDM-AP)";
t->attach = (void*)nop_function;
t->detach = (void*)nop_function;
t->check_error = (void*)nop_function;
t->mem_read = (void*)nop_function;
t->mem_write = (void*)nop_function;
t->regs_size = 4;
t->regs_read = (void*)nop_function;
t->regs_write = (void*)nop_function;
t->reset = (void*)nop_function;
t->halt_request = (void*)nop_function;
t->halt_poll = mdm_halt_poll;
t->halt_resume = (void*)nop_function;
target_add_commands(t, kinetis_mdm_cmd_list, t->driver);
}
bool msp432_probe(target *t)
{
/* Check for the right device info tag in the TLV ROM structure */
if (target_mem_read32(t, DEVINFO_TAG_ADDR) != DEVINFO_TAG_VALUE)
return false;
/* Check for the right device info length tag in the TLV ROM structure */
if (target_mem_read32(t, DEVINFO_LEN_ADDR) != DEVINFO_LEN_VALUE)
return false;
/* Check for the right HW revision: at least C, as no flash support for B */
if (target_mem_read32(t, HWREV_ADDR) < HWREV_MIN_VALUE)
return false;
/* If we got till this point, we are most probably looking at a real TLV */
/* Device Information structure. Now check for the correct device */
switch (target_mem_read32(t, DEVID_ADDR)) {
case DEVID_MSP432P401RIPZ:
case DEVID_MSP432P401RIZXH:
case DEVID_MSP432P401RIRGC:
/* R series: 256kB Flash, 64kB RAM */
t->driver = "MSP432P401R 256KB Flash 64KB RAM";
break;
case DEVID_MSP432P401MIPZ:
case DEVID_MSP432P401MIZXH:
case DEVID_MSP432P401MIRGC:
/* M series: 128kB Flash, 32kB RAM */
t->driver = "MSP432P401M 128KB Flash 32KB RAM";
break;
default:
/* Unknown device, not an MSP432 or not a real TLV */
return false;
}
/* SRAM region, SRAM zone */
target_add_ram(t, SRAM_BASE, target_mem_read32(t, SYS_SRAM_SIZE));
/* Flash bank size */
uint32_t banksize = target_mem_read32(t, SYS_FLASH_SIZE) / 2;
/* Main Flash Bank 0 */
msp432_add_flash(t, MAIN_FLASH_BASE, banksize, MAIN_BANK0_WEPROT);
/* Main Flash Bank 1 */
msp432_add_flash(t, MAIN_FLASH_BASE + banksize, banksize, MAIN_BANK1_WEPROT);
/* Info Flash Bank 0 */
msp432_add_flash(t, INFO_FLASH_BASE, INFO_BANK_SIZE, INFO_BANK0_WEPROT);
/* Info Flash Bank 1 */
msp432_add_flash(t, INFO_FLASH_BASE + INFO_BANK_SIZE, INFO_BANK_SIZE, INFO_BANK1_WEPROT);
/* Connect the optional commands */
target_add_commands(t, msp432_cmd_list, "MSP432P401x");
/* All done */
return true;
}
bool stm32f4_probe(struct target_s *target)
{
uint32_t idcode;
idcode = adiv5_ap_mem_read(adiv5_target_ap(target), DBGMCU_IDCODE);
switch(idcode & 0xFFF) {
case 0x411: /* Documented to be 0x413! This is what I read... */
case 0x413:
case 0x423: /* F401 */
case 0x419: /* 427/437 */
target->driver = stm32f4_driver_str;
target->xml_mem_map = stm32f4_xml_memory_map;
target->flash_erase = stm32f4_flash_erase;
target->flash_write = stm32f4_flash_write;
target_add_commands(target, stm32f4_cmd_list, "STM32F4");
return true;
}
return false;
}
bool stm32l4_probe(target *t)
{
uint32_t idcode;
uint32_t size;
uint32_t options;
uint32_t bank1_start = 0x08040000;
idcode = target_mem_read32(t, DBGMCU_IDCODE);
switch(idcode & 0xFFF) {
case 0x415: /* */
t->driver = stm32l4_driver_str;
target_add_ram(t, 0x10000000, 1 << 15);
target_add_ram(t, 0x20000000, 3 << 15);
size = (target_mem_read32(t, FLASH_SIZE_REG) & 0xffff);
options = target_mem_read32(t, FLASH_OPTR);
if ((size < 0x400) && (options & OR_DUALBANK))
bank1_start = 0x08000000 + (size << 9);
stm32l4_add_flash(t, 0x08000000, size << 10, PAGE_SIZE, bank1_start);
target_add_commands(t, stm32l4_cmd_list, "STM32L4");
return true;
}
return false;
}
bool stm32f1_probe(target *t)
{
size_t flash_size;
size_t block_size = 0x400;
t->idcode = target_mem_read32(t, DBGMCU_IDCODE) & 0xfff;
switch(t->idcode) {
case 0x410: /* Medium density */
case 0x412: /* Low denisty */
case 0x420: /* Value Line, Low-/Medium density */
t->driver = "STM32F1 medium density";
target_add_ram(t, 0x20000000, 0x5000);
stm32f1_add_flash(t, 0x8000000, 0x20000, 0x400);
target_add_commands(t, stm32f1_cmd_list, "STM32 LD/MD");
return true;
case 0x414: /* High density */
case 0x418: /* Connectivity Line */
case 0x428: /* Value Line, High Density */
t->driver = "STM32F1 high density";
target_add_ram(t, 0x20000000, 0x10000);
stm32f1_add_flash(t, 0x8000000, 0x80000, 0x800);
target_add_commands(t, stm32f1_cmd_list, "STM32 HD/CL");
return true;
case 0x438: /* STM32F303x6/8 and STM32F328 */
case 0x422: /* STM32F30x */
case 0x446: /* STM32F303xD/E and STM32F398xE */
target_add_ram(t, 0x10000000, 0x4000);
/* fall through */
case 0x432: /* STM32F37x */
case 0x439: /* STM32F302C8 */
t->driver = "STM32F3";
target_add_ram(t, 0x20000000, 0x10000);
stm32f1_add_flash(t, 0x8000000, 0x80000, 0x800);
target_add_commands(t, stm32f1_cmd_list, "STM32F3");
return true;
}
t->idcode = target_mem_read32(t, DBGMCU_IDCODE_F0) & 0xfff;
switch(t->idcode) {
case 0x444: /* STM32F03 RM0091 Rev.7, STM32F030x[4|6] RM0360 Rev. 4*/
t->driver = "STM32F03";
flash_size = 0x8000;
break;
case 0x445: /* STM32F04 RM0091 Rev.7, STM32F070x6 RM0360 Rev. 4*/
t->driver = "STM32F04/F070x6";
flash_size = 0x8000;
break;
case 0x440: /* STM32F05 RM0091 Rev.7, STM32F030x8 RM0360 Rev. 4*/
t->driver = "STM32F05/F030x8";
flash_size = 0x10000;
break;
case 0x448: /* STM32F07 RM0091 Rev.7, STM32F070xB RM0360 Rev. 4*/
t->driver = "STM32F07";
flash_size = 0x20000;
block_size = 0x800;
break;
case 0x442: /* STM32F09 RM0091 Rev.7, STM32F030xC RM0360 Rev. 4*/
t->driver = "STM32F09/F030xC";
flash_size = 0x40000;
block_size = 0x800;
break;
default: /* NONE */
return false;
}
target_add_ram(t, 0x20000000, 0x5000);
stm32f1_add_flash(t, 0x8000000, flash_size, block_size);
target_add_commands(t, stm32f1_cmd_list, "STM32F0");
return true;
}
bool nrf51_probe(target *t)
{
t->idcode = target_mem_read32(t, NRF51_FICR_CONFIGID) & 0xFFFF;
switch (t->idcode) {
case 0x001D: /* nRF51822 (rev 1) QFAA CA/C0 */
case 0x001E: /* nRF51422 (rev 1) QFAA CA */
case 0x0020: /* nRF51822 (rev 1) CEAA BA */
case 0x0024: /* nRF51422 (rev 1) QFAA C0 */
case 0x002A: /* nRF51822 (rev 2) QFAA FA0 */
case 0x004A: /* nRF51822 (rev 3) QFAA G1 */
case 0x002D: /* nRF51422 (rev 2) QFAA DAA */
case 0x002E: /* nRF51422 (rev 2) QFAA E0 */
case 0x002F: /* nRF51822 (rev 1) CEAA B0 */
case 0x0031: /* nRF51422 (rev 1) CEAA A0A */
case 0x003C: /* nRF51822 (rev 2) QFAA G0 */
case 0x0057: /* nRF51422 (rev 2) QFAA G2 */
case 0x0040: /* nRF51822 (rev 2) CEAA CA0 */
case 0x0044: /* nRF51822 (rev 2) QFAA GC0 */
case 0x0047: /* nRF51822 (rev 2) CEAA DA0 */
case 0x004D: /* nRF51822 (rev 2) CEAA D00 */
case 0x0050: /* nRF51422 (rev 2) CEAA B0 */
case 0x0072: /* nRF51822 (rev 3) QFAA H0 */
case 0x0073: /* nRF51422 (rev 3) QFAA F0 */
case 0x0079: /* nRF51822 (rev 3) CEAA E0 */
case 0x007A: /* nRF51422 (rev 3) CEAA C0 */
case 0x008F: /* nRF51822 (rev 3) QFAA H1 See https://devzone.nordicsemi.com/question/97769/can-someone-conform-the-config-id-code-for-the-nrf51822qfaah1/ */
case 0x00D1: /* nRF51822 (rev 3) QFAA H2 */
case 0x0114: /* nRF51802 (rev ?) QFAA A1 */
t->driver = "Nordic nRF51";
target_add_ram(t, 0x20000000, 0x4000);
nrf51_add_flash(t, 0x00000000, 0x40000, NRF51_PAGE_SIZE);
nrf51_add_flash(t, NRF51_UICR, 0x100, 0x100);
target_add_commands(t, nrf51_cmd_list, "nRF51");
return true;
case 0x0026: /* nRF51822 (rev 1) QFAB AA */
case 0x0027: /* nRF51822 (rev 1) QFAB A0 */
case 0x004C: /* nRF51822 (rev 2) QFAB B0 */
case 0x0061: /* nRF51422 (rev 2) QFAB A00 */
case 0x007B: /* nRF51822 (rev 3) QFAB C0 */
case 0x007C: /* nRF51422 (rev 3) QFAB B0 */
case 0x007D: /* nRF51822 (rev 3) CDAB A0 */
case 0x007E: /* nRF51422 (rev 3) CDAB A0 */
t->driver = "Nordic nRF51";
target_add_ram(t, 0x20000000, 0x4000);
nrf51_add_flash(t, 0x00000000, 0x20000, NRF51_PAGE_SIZE);
nrf51_add_flash(t, NRF51_UICR, 0x100, 0x100);
target_add_commands(t, nrf51_cmd_list, "nRF51");
return true;
case 0x0071: /* nRF51422 (rev 3) QFAC AB */
case 0x0083: /* nRF51822 (rev 3) QFAC A0 */
case 0x0084: /* nRF51422 (rev 3) QFAC A1 */
case 0x0085: /* nRF51422 (rev 3) QFAC A0 */
case 0x0086: /* nRF51422 (rev 3) QFAC A1 */
case 0x0087: /* nRF51822 (rev 3) CFAC A0 */
case 0x0088: /* nRF51422 (rev 3) CFAC A0 */
t->driver = "Nordic nRF51";
target_add_ram(t, 0x20000000, 0x8000);
nrf51_add_flash(t, 0x00000000, 0x40000, NRF51_PAGE_SIZE);
nrf51_add_flash(t, NRF51_UICR, 0x100, 0x100);
target_add_commands(t, nrf51_cmd_list, "nRF51");
return true;
case 0x00AC: /* nRF52832 Preview QFAA BA0 */
case 0x00C7: /* nRF52832 Revision 1 QFAA B00 */
case 0x00E3: /* nRF52832-CIAA CSP */
t->driver = "Nordic nRF52";
target_add_ram(t, 0x20000000, 64*1024);
nrf51_add_flash(t, 0x00000000, 512*1024, NRF52_PAGE_SIZE);
nrf51_add_flash(t, NRF51_UICR, 0x100, 0x100);
target_add_commands(t, nrf51_cmd_list, "nRF52");
return true;
case 0x00EB: /* nRF52840 Preview QIAA AA0 */
t->driver = "Nordic nRF52";
target_add_ram(t, 0x20000000, 256*1024);
nrf51_add_flash(t, 0x00000000, 1024*1024, NRF52_PAGE_SIZE);
nrf51_add_flash(t, NRF51_UICR, 0x100, 0x100);
target_add_commands(t, nrf51_cmd_list, "nRF52");
return true;
}
return false;
}
bool sam3x_probe(target *t)
{
t->idcode = target_mem_read32(t, SAM3X_CHIPID_CIDR);
size_t size = sam_flash_size(t->idcode);
switch (t->idcode & (CHIPID_CIDR_ARCH_MASK | CHIPID_CIDR_EPROC_MASK)) {
case CHIPID_CIDR_ARCH_SAM3XxC | CHIPID_CIDR_EPROC_CM3:
case CHIPID_CIDR_ARCH_SAM3XxE | CHIPID_CIDR_EPROC_CM3:
case CHIPID_CIDR_ARCH_SAM3XxG | CHIPID_CIDR_EPROC_CM3:
t->driver = "Atmel SAM3X";
target_add_ram(t, 0x20000000, 0x200000);
/* 2 Flash memories back-to-back starting at 0x80000 */
sam3_add_flash(t, SAM3X_EEFC_BASE(0), 0x80000, size/2);
sam3_add_flash(t, SAM3X_EEFC_BASE(1), 0x80000 + size/2, size/2);
target_add_commands(t, sam3x_cmd_list, "SAM3X");
return true;
}
t->idcode = target_mem_read32(t, SAM34NSU_CHIPID_CIDR);
size = sam_flash_size(t->idcode);
switch (t->idcode & (CHIPID_CIDR_ARCH_MASK | CHIPID_CIDR_EPROC_MASK)) {
case CHIPID_CIDR_ARCH_SAM3NxA | CHIPID_CIDR_EPROC_CM3:
case CHIPID_CIDR_ARCH_SAM3NxB | CHIPID_CIDR_EPROC_CM3:
case CHIPID_CIDR_ARCH_SAM3NxC | CHIPID_CIDR_EPROC_CM3:
case CHIPID_CIDR_ARCH_SAM3SxA | CHIPID_CIDR_EPROC_CM3:
case CHIPID_CIDR_ARCH_SAM3SxB | CHIPID_CIDR_EPROC_CM3:
case CHIPID_CIDR_ARCH_SAM3SxC | CHIPID_CIDR_EPROC_CM3:
t->driver = "Atmel SAM3N/S";
target_add_ram(t, 0x20000000, 0x200000);
/* These devices only have a single bank */
size = sam_flash_size(t->idcode);
sam3_add_flash(t, SAM3N_EEFC_BASE, 0x400000, size);
target_add_commands(t, sam3x_cmd_list, "SAM3N/S");
return true;
case CHIPID_CIDR_ARCH_SAM3UxC | CHIPID_CIDR_EPROC_CM3:
case CHIPID_CIDR_ARCH_SAM3UxE | CHIPID_CIDR_EPROC_CM3:
t->driver = "Atmel SAM3U";
target_add_ram(t, 0x20000000, 0x200000);
/* One flash up to 512K at 0x80000 */
sam3_add_flash(t, SAM3U_EEFC_BASE(0), 0x80000, MIN(size, 0x80000));
if (size >= 0x80000) {
/* Larger devices have a second bank at 0x100000 */
sam3_add_flash(t, SAM3U_EEFC_BASE(1),
0x100000, 0x80000);
}
target_add_commands(t, sam3x_cmd_list, "SAM3U");
return true;
case CHIPID_CIDR_ARCH_SAM4SxA | CHIPID_CIDR_EPROC_CM4:
case CHIPID_CIDR_ARCH_SAM4SxB | CHIPID_CIDR_EPROC_CM4:
case CHIPID_CIDR_ARCH_SAM4SxC | CHIPID_CIDR_EPROC_CM4:
t->driver = "Atmel SAM4S";
target_add_ram(t, 0x20000000, 0x400000);
size_t size = sam_flash_size(t->idcode);
if (size <= 0x80000) {
/* Smaller devices have a single bank */
sam4_add_flash(t, SAM4S_EEFC_BASE(0), 0x400000, size);
} else {
/* Larger devices are split evenly between 2 */
sam4_add_flash(t, SAM4S_EEFC_BASE(0), 0x400000, size/2);
sam4_add_flash(t, SAM4S_EEFC_BASE(1),
0x400000 + size/2, size/2);
}
target_add_commands(t, sam3x_cmd_list, "SAM4S");
return true;
}
return false;
}
bool efm32_probe(target *t)
{
/* Read the IDCODE register from the SW-DP */
ADIv5_AP_t *ap = cortexm_ap(t);
uint32_t ap_idcode = ap->dp->idcode;
/* Check the idcode is silabs. See AN0062 Section 2.2 */
if (ap_idcode == 0x2BA01477) {
/* Cortex M3, Cortex M4 */
} else if (ap_idcode == 0x0BC11477) {
/* Cortex M0+ */
} else {
return false;
}
/* Read the part number and family */
uint16_t part_number = efm32_read_part_number(t);
uint8_t part_family = efm32_read_part_family(t);
uint16_t radio_number, radio_number_short; /* optional, for ezr parts */
uint32_t flash_page_size; uint16_t flash_kb;
switch(part_family) {
case EFM32_DI_PART_FAMILY_GECKO:
sprintf(variant_string,
"EFM32 Gecko");
flash_page_size = 512;
break;
case EFM32_DI_PART_FAMILY_GIANT_GECKO:
sprintf(variant_string,
"EFM32 Giant Gecko");
flash_page_size = 2048; /* Could be 2048 or 4096, assume 2048 */
break;
case EFM32_DI_PART_FAMILY_TINY_GECKO:
sprintf(variant_string,
"EFM32 Tiny Gecko");
flash_page_size = 512;
break;
case EFM32_DI_PART_FAMILY_LEOPARD_GECKO:
sprintf(variant_string,
"EFM32 Leopard Gecko");
flash_page_size = 2048; /* Could be 2048 or 4096, assume 2048 */
break;
case EFM32_DI_PART_FAMILY_WONDER_GECKO:
sprintf(variant_string,
"EFM32 Wonder Gecko");
flash_page_size = 2048;
break;
case EFM32_DI_PART_FAMILY_ZERO_GECKO:
sprintf(variant_string,
"EFM32 Zero Gecko");
flash_page_size = 1024;
break;
case EFM32_DI_PART_FAMILY_HAPPY_GECKO:
sprintf(variant_string,
"EFM32 Happy Gecko");
flash_page_size = 1024;
break;
case EFM32_DI_PART_FAMILY_EZR_WONDER_GECKO:
radio_number = efm32_read_radio_part_number(t); /* on-chip radio */
radio_number_short = radio_number % 100;
flash_kb = efm32_read_flash_size(t);
sprintf(variant_string,
"EZR32WG%dF%dR%d (radio si%d)",
part_number, flash_kb,
radio_number_short, radio_number);
flash_page_size = 2048;
break;
case EFM32_DI_PART_FAMILY_EZR_LEOPARD_GECKO:
radio_number = efm32_read_radio_part_number(t); /* on-chip radio */
radio_number_short = radio_number % 100;
flash_kb = efm32_read_flash_size(t);
sprintf(variant_string,
"EZR32LG%dF%dR%d (radio si%d)",
part_number, flash_kb,
radio_number_short, radio_number);
flash_page_size = 2048;
break;
default: /* Unknown family */
return false;
}
/* Read memory sizes, convert to bytes */
uint32_t flash_size = efm32_read_flash_size(t) * 0x400;
uint32_t ram_size = efm32_read_ram_size(t) * 0x400;
/* Setup Target */
t->target_options |= CORTEXM_TOPT_INHIBIT_SRST;
t->driver = variant_string;
tc_printf(t, "flash size %d page size %d\n", flash_size, flash_page_size);
target_add_ram (t, SRAM_BASE, ram_size);
efm32_add_flash(t, 0x00000000, flash_size, flash_page_size);
target_add_commands(t, efm32_cmd_list, "EFM32");
return true;
}
bool kinetis_probe(target *t)
{
uint32_t sdid = target_mem_read32(t, SIM_SDID);
switch (sdid >> 20) {
case 0x251:
t->driver = "KL25";
target_add_ram(t, 0x1ffff000, 0x1000);
target_add_ram(t, 0x20000000, 0x3000);
kl_gen_add_flash(t, 0x00000000, 0x20000, 0x400, KL_WRITE_LEN);
break;
case 0x231:
t->driver = "KL27x128"; // MKL27 >=128kb
target_add_ram(t, 0x1fffe000, 0x2000);
target_add_ram(t, 0x20000000, 0x6000);
kl_gen_add_flash(t, 0x00000000, 0x40000, 0x400, KL_WRITE_LEN);
break;
case 0x271:
switch((sdid>>16)&0x0f){
case 4:
t->driver = "KL27x32";
target_add_ram(t, 0x1ffff800, 0x0800);
target_add_ram(t, 0x20000000, 0x1800);
kl_gen_add_flash(t, 0x00000000, 0x8000, 0x400, KL_WRITE_LEN);
break;
case 5:
t->driver = "KL27x64";
target_add_ram(t, 0x1ffff000, 0x1000);
target_add_ram(t, 0x20000000, 0x3000);
kl_gen_add_flash(t, 0x00000000, 0x10000, 0x400, KL_WRITE_LEN);
break;
default:
return false;
}
break;
case 0x021: /* KL02 family */
switch((sdid>>16) & 0x0f){
case 3:
t->driver = "KL02x32";
target_add_ram(t, 0x1FFFFC00, 0x400);
target_add_ram(t, 0x20000000, 0xc00);
kl_gen_add_flash(t, 0x00000000, 0x7FFF, 0x400, KL_WRITE_LEN);
break;
case 2:
t->driver = "KL02x16";
target_add_ram(t, 0x1FFFFE00, 0x200);
target_add_ram(t, 0x20000000, 0x600);
kl_gen_add_flash(t, 0x00000000, 0x3FFF, 0x400, KL_WRITE_LEN);
break;
case 1:
t->driver = "KL02x8";
target_add_ram(t, 0x1FFFFF00, 0x100);
target_add_ram(t, 0x20000000, 0x300);
kl_gen_add_flash(t, 0x00000000, 0x1FFF, 0x400, KL_WRITE_LEN);
break;
default:
return false;
}
break;
case 0x031: /* KL03 family */
t->driver = "KL03";
target_add_ram(t, 0x1ffffe00, 0x200);
target_add_ram(t, 0x20000000, 0x600);
kl_gen_add_flash(t, 0, 0x8000, 0x400, KL_WRITE_LEN);
break;
case 0x220: /* K22F family */
t->driver = "K22F";
target_add_ram(t, 0x1c000000, 0x4000000);
target_add_ram(t, 0x20000000, 0x100000);
kl_gen_add_flash(t, 0, 0x40000, 0x800, KL_WRITE_LEN);
kl_gen_add_flash(t, 0x40000, 0x40000, 0x800, KL_WRITE_LEN);
break;
case 0x620: /* K64F family. */
/* This should be 0x640, but according to the errata sheet
* (KINETIS_1N83J) K64 and K24's will show up with the
* subfamily nibble as 2
*/
t->driver = "K64";
target_add_ram(t, 0x1FFF0000, 0x10000);
target_add_ram(t, 0x20000000, 0x30000);
kl_gen_add_flash(t, 0, 0x80000, 0x1000, K64_WRITE_LEN);
kl_gen_add_flash(t, 0x80000, 0x80000, 0x1000, K64_WRITE_LEN);
break;
default:
return false;
}
unsafe_enabled = false;
target_add_commands(t, kinetis_cmd_list, t->driver);
return true;
}
bool stm32f1_probe(target *t)
{
size_t flash_size;
size_t block_size = 0x400;
t->idcode = target_mem_read32(t, DBGMCU_IDCODE) & 0xfff;
switch(t->idcode) {
case 0x410: /* Medium density */
case 0x412: /* Low denisty */
case 0x420: /* Value Line, Low-/Medium density */
t->driver = "STM32F1 medium density";
target_add_ram(t, 0x20000000, 0x5000);
stm32f1_add_flash(t, 0x8000000, 0x20000, 0x400);
target_add_commands(t, stm32f1_cmd_list, "STM32 LD/MD");
return true;
case 0x414: /* High density */
case 0x418: /* Connectivity Line */
case 0x428: /* Value Line, High Density */
t->driver = "STM32F1 high density";
target_add_ram(t, 0x20000000, 0x10000);
stm32f1_add_flash(t, 0x8000000, 0x80000, 0x800);
target_add_commands(t, stm32f1_cmd_list, "STM32 HD/CL");
return true;
case 0x422: /* STM32F30x */
case 0x432: /* STM32F37x */
case 0x439: /* STM32F302C8 */
t->driver = "STM32F3";
target_add_ram(t, 0x20000000, 0x10000);
stm32f1_add_flash(t, 0x8000000, 0x80000, 0x800);
target_add_commands(t, stm32f1_cmd_list, "STM32F3");
return true;
}
t->idcode = target_mem_read32(t, DBGMCU_IDCODE_F0) & 0xfff;
switch(t->idcode) {
case 0x444: /* STM32F03 RM0091 Rev.7 */
t->driver = "STM32F03";
break;
case 0x445: /* STM32F04 RM0091 Rev.7 */
t->driver = "STM32F04";
break;
case 0x440: /* STM32F05 RM0091 Rev.7 */
t->driver = "STM32F05";
break;
case 0x448: /* STM32F07 RM0091 Rev.7 */
t->driver = "STM32F07";
block_size = 0x800;
break;
case 0x442: /* STM32F09 RM0091 Rev.7 */
t->driver = "STM32F09";
block_size = 0x800;
break;
default: /* NONE */
return false;
}
flash_size = (target_mem_read32(t, FLASHSIZE_F0) & 0xffff) *0x400;
tc_printf(t, "flash size %d block_size %d\n", flash_size, block_size);
target_add_ram(t, 0x20000000, 0x5000);
stm32f1_add_flash(t, 0x8000000, flash_size, block_size);
target_add_commands(t, stm32f1_cmd_list, "STM32F0");
return true;
}
bool nrf51_probe(target *t)
{
t->idcode = target_mem_read32(t, NRF51_FICR_CONFIGID) & 0xFFFF;
switch (t->idcode) {
case 0x001D: /* nRF51822 (rev 1) QFAA CA/C0 */
case 0x001E: /* nRF51422 (rev 1) QFAA CA */
case 0x0020: /* nRF51822 (rev 1) CEAA BA */
case 0x0024: /* nRF51422 (rev 1) QFAA C0 */
case 0x002A: /* nRF51822 (rev 2) QFAA FA0 */
case 0x002D: /* nRF51422 (rev 2) QFAA DAA */
case 0x002E: /* nRF51422 (rev 2) QFAA E0 */
case 0x002F: /* nRF51822 (rev 1) CEAA B0 */
case 0x0031: /* nRF51422 (rev 1) CEAA A0A */
case 0x003C: /* nRF51822 (rev 2) QFAA G0 */
case 0x0040: /* nRF51822 (rev 2) CEAA CA0 */
case 0x0044: /* nRF51822 (rev 2) QFAA GC0 */
case 0x0047: /* nRF51822 (rev 2) CEAA DA0 */
case 0x004D: /* nRF51822 (rev 2) CEAA D00 */
case 0x0050: /* nRF51422 (rev 2) CEAA B0 */
case 0x0072: /* nRF51822 (rev 3) QFAA H0 */
case 0x0073: /* nRF51422 (rev 3) QFAA F0 */
case 0x0079: /* nRF51822 (rev 3) CEAA E0 */
case 0x007A: /* nRF51422 (rev 3) CEAA C0 */
t->driver = "Nordic nRF51";
target_add_ram(t, 0x20000000, 0x4000);
nrf51_add_flash(t, 0x00000000, 0x40000, NRF51_PAGE_SIZE);
nrf51_add_flash(t, NRF51_UICR, 0x100, 0x100);
target_add_commands(t, nrf51_cmd_list, "nRF51");
return true;
case 0x0026: /* nRF51822 (rev 1) QFAB AA */
case 0x0027: /* nRF51822 (rev 1) QFAB A0 */
case 0x004C: /* nRF51822 (rev 2) QFAB B0 */
case 0x0061: /* nRF51422 (rev 2) QFAB A00 */
case 0x007B: /* nRF51822 (rev 3) QFAB C0 */
case 0x007C: /* nRF51422 (rev 3) QFAB B0 */
case 0x007D: /* nRF51822 (rev 3) CDAB A0 */
case 0x007E: /* nRF51422 (rev 3) CDAB A0 */
t->driver = "Nordic nRF51";
target_add_ram(t, 0x20000000, 0x4000);
nrf51_add_flash(t, 0x00000000, 0x20000, NRF51_PAGE_SIZE);
nrf51_add_flash(t, NRF51_UICR, 0x100, 0x100);
target_add_commands(t, nrf51_cmd_list, "nRF51");
return true;
case 0x0071: /* nRF51422 (rev 3) QFAC AB */
case 0x0083: /* nRF51822 (rev 3) QFAC A0 */
case 0x0084: /* nRF51422 (rev 3) QFAC A1 */
case 0x0085: /* nRF51422 (rev 3) QFAC A0 */
case 0x0086: /* nRF51422 (rev 3) QFAC A1 */
case 0x0087: /* nRF51822 (rev 3) CFAC A0 */
case 0x0088: /* nRF51422 (rev 3) CFAC A0 */
t->driver = "Nordic nRF51";
target_add_ram(t, 0x20000000, 0x8000);
nrf51_add_flash(t, 0x00000000, 0x40000, NRF51_PAGE_SIZE);
nrf51_add_flash(t, NRF51_UICR, 0x100, 0x100);
target_add_commands(t, nrf51_cmd_list, "nRF51");
return true;
}
return false;
}
bool stm32f4_probe(target *t)
{
bool f2 = false;
uint32_t idcode;
idcode = target_mem_read32(t, DBGMCU_IDCODE);
idcode &= 0xFFF;
if (idcode == ID_STM32F20X)
{
/* F405 revision A have a wrong IDCODE, use ARM_CPUID to make the
* distinction with F205. Revision is also wrong (0x2000 instead
* of 0x1000). See F40x/F41x errata. */
uint32_t cpuid = target_mem_read32(t, ARM_CPUID);
if ((cpuid & 0xFFF0) == 0xC240)
idcode = ID_STM32F40X;
else
f2 = true;
}
switch(idcode) {
case ID_STM32F42X: /* 427/437 */
case ID_STM32F46X: /* 469/479 */
/* Second bank for 2M parts. */
stm32f4_add_flash(t, 0x8100000, 0x10000, 0x4000, 12);
stm32f4_add_flash(t, 0x8110000, 0x10000, 0x10000, 16);
stm32f4_add_flash(t, 0x8120000, 0xE0000, 0x20000, 17);
/* Fall through for stuff common to F40x/F41x */
case ID_STM32F20X: /* F205 */
case ID_STM32F40X: /* F405 */
if (!f2)
target_add_ram(t, 0x10000000, 0x10000);
/* Fall through for devices w/o CCMRAM */
case ID_STM32F446: /* F446 */
case ID_STM32F401C: /* F401 B/C RM0368 Rev.3 */
case ID_STM32F411: /* F411 RM0383 Rev.4 */
case ID_STM32F412: /* F412 RM0402 Rev.4, 256 kB Ram */
case ID_STM32F401E: /* F401 D/E RM0368 Rev.3 */
t->driver = f2 ? stm32f2_driver_str : stm32f4_driver_str;
target_add_ram(t, 0x20000000, 0x40000);
stm32f4_add_flash(t, 0x8000000, 0x10000, 0x4000, 0);
stm32f4_add_flash(t, 0x8010000, 0x10000, 0x10000, 4);
stm32f4_add_flash(t, 0x8020000, 0xE0000, 0x20000, 5);
target_add_commands(t, stm32f4_cmd_list, f2 ? "STM32F2" :
"STM32F4");
break;
case ID_STM32F413: /* F413 RM0430 Rev.2, 320 kB Ram, 1.5 MB flash. */
t->driver = stm32f4_driver_str;
target_add_ram(t, 0x20000000, 0x50000);
stm32f4_add_flash(t, 0x8000000, 0x10000, 0x4000, 0);
stm32f4_add_flash(t, 0x8010000, 0x10000, 0x10000, 4);
stm32f4_add_flash(t, 0x8020000, 0x160000, 0x20000, 5);
target_add_commands(t, stm32f4_cmd_list, "STM32F413");
break;
case ID_STM32F74X: /* F74x RM0385 Rev.4 */
t->driver = stm32f7_driver_str;
target_add_ram(t, 0x00000000, 0x4000);
target_add_ram(t, 0x20000000, 0x50000);
/* AXIM Flash access */
stm32f4_add_flash(t, 0x8000000, 0x20000, 0x8000, 0);
stm32f4_add_flash(t, 0x8020000, 0x20000, 0x20000, 4);
stm32f4_add_flash(t, 0x8040000, 0xC0000, 0x40000, 5);
/* Flash aliased as ITCM */
stm32f4_add_flash(t, 0x0200000, 0x20000, 0x8000, 0);
stm32f4_add_flash(t, 0x0220000, 0x20000, 0x20000, 4);
stm32f4_add_flash(t, 0x0240000, 0xC0000, 0x40000, 5);
target_add_commands(t, stm32f4_cmd_list, "STM32F74x");
break;
case ID_STM32F76X: /* F76x F77x RM0410 */
t->driver = stm32f7_driver_str;
target_add_ram(t, 0x00000000, 0x4000);
target_add_ram(t, 0x20000000, 0x80000);
/* AXIM Flash access */
stm32f4_add_flash(t, 0x8000000, 0x020000, 0x8000, 0);
stm32f4_add_flash(t, 0x8020000, 0x020000, 0x20000, 4);
stm32f4_add_flash(t, 0x8040000, 0x1C0000, 0x40000, 5);
/* Flash aliased as ITCM */
stm32f4_add_flash(t, 0x200000, 0x020000, 0x8000, 0);
stm32f4_add_flash(t, 0x220000, 0x020000, 0x20000, 4);
stm32f4_add_flash(t, 0x240000, 0x1C0000, 0x40000, 5);
target_add_commands(t, stm32f4_cmd_list, "STM32F76x");
break;
case ID_STM32F72X: /* F72x F73x RM0431 */
t->driver = stm32f7_driver_str;
target_add_ram(t, 0x00000000, 0x2000);
target_add_ram(t, 0x20000000, 0x40000);
stm32f4_add_flash(t, 0x8000000, 0x010000, 0x4000, 0);
stm32f4_add_flash(t, 0x8010000, 0x010000, 0x10000, 4);
stm32f4_add_flash(t, 0x8020000, 0x060000, 0x20000, 3);
target_add_commands(t, stm32f4_cmd_list, "STM32F72x");
break;
default:
return false;
}
t->idcode = idcode;
return true;
}
