void TimerE1_init(void)
{
tc_write_clock_source(&TCE1,TC_CLKSEL_DIV256_gc);
tc_set_wgm(&TCE1,TC_WG_SS);
tc_write_period(&TCE1,0x00FF);
tc_set_direction(&TCE1,TC_UP);
tc_enable_cc_channels(&TCE1,TC_CCAEN);
tc_enable(&TCE1);
};
void TimerD0_init(void)
{
tc_write_clock_source(&TCD0,TC_CLKSEL_DIV256_gc);
tc_set_wgm(&TCD0,TC_WG_NORMAL);
tc_set_overflow_interrupt_level(&TCD0,TC_INT_LVL_MED);
tc_write_period(&TCD0,TIMERD0_PER);
tc_set_direction(&TCD0,TC_UP);
tc_enable(&TCD0);
};
void TimerC0_init(void)
{
tc_write_clock_source(&TCC0,TC_CLKSEL_DIV64_gc);//1
tc_set_wgm(&TCC0,TC_WG_SS);
tc_write_period(&TCC0,0x77);//0x01DFF
tc_set_direction(&TCC0,TC_UP);
tc_enable_cc_channels(&TCC0,TC_CCAEN);
tc_enable_cc_channels(&TCC0,TC_CCBEN);
tc_enable(&TCC0);
tc_write_cc(&TCC0,TC_CCA,0x5D);
};
void app_cpu_load_init(void)
{
/* Reset counters */
app_cpu_load_time_actif = 0;
app_cpu_load_time_sleep = 0;
/* Start Timer counter used to monitor CPU timing */
tc_enable(&TCC1);
tc_write_clock_source(&TCC1, TC_CLKSEL_DIV256_gc); /* 24MHz / 256 */
tc_set_direction(&TCC1, TC_UP);
/* Display static background */
gfx_mono_draw_string(DISPLAY_CPU_LOAD_TEXT,
DISPLAY_CPU_LOAD_TEXT_POS_X,
DISPLAY_CPU_LOAD_TEXT_POS_Y,
&sysfont);
}
/**
* \brief Delay function which use a Timer Counter and can be aborted
* SW1 pressed stop delay.
*
* \param delay_ms delay in ms
*/
static void main_introduction_delay(uint16_t delay_ms)
{
/* Initialization TC to manage a delay between each slide */
tc_enable(&TCC1);
tc_write_clock_source(&TCC1, TC_CLKSEL_DIV1024_gc); /* 24MHz / 1024 */
tc_set_direction(&TCC1, TC_UP);
while (delay_ms) {
tc_write_count(&TCC1, 0);
uint16_t delay_step = delay_ms;
if (delay_step > 2800) {
delay_step = 2500;
}
while (tc_read_count(&TCC1) <
((24000lu * delay_step) / 1024lu)) {
if (main_introduction_is_exist()) {
break;
}
}
delay_ms -= delay_step;
}
tc_disable(&TCC1);
}
/**
* \brief Test read from fixed location, trigger from timer and callback
*
* \note This test sets up a timer to trigger the DMA module,
* which in turn reads the timer_overflow_counter variable and writes
* it to memory sequentially. It then checks to see that the memory block
* written is sequential according to the overflow count.
*
* \param test Current test
*/
static void run_dma_triggered_with_callback(const struct test_case *test)
{
struct dma_channel_config config_params;
bool success;
/* Null the buffer */
set_buffer(dest_block_tc, 0x0000);
/* Null out the config parameter struct */
memset(&config_params, 0, sizeof(config_params));
/*
* Enable the timer, and set it to count up.
* When it overflows, it triggers the DMA to
* read timer_overflow_counter. */
tc_enable(&TIMER);
tc_set_direction(&TIMER, TC_UP);
tc_write_period(&TIMER, TIMER_PERIOD);
tc_set_resolution(&TIMER, TIMER_RESOLUTION);
tc_set_overflow_interrupt_level(&TIMER, PMIC_LVL_LOW);
tc_set_overflow_interrupt_callback(&TIMER, timer_overflow_callback);
/* Enable the DMA module */
dma_enable();
/* Set callback for transfer done */
dma_set_callback(DMA_CHANNEL_0, dma_transfer_is_complete);
/* Set low interrupt level */
dma_channel_set_interrupt_level(&config_params, PMIC_LVL_LOW);
/* Set up the DMA to read the timer value
*
* - Single shot transfer mode
* - Two byte (16-bit) burst length
* - Increment on source and destination
* - Reload on burst for source
* - No reload for destination
*/
dma_channel_set_single_shot(&config_params);
dma_channel_set_burst_length(&config_params,
DMA_CH_BURSTLEN_1BYTE_gc);
dma_channel_set_src_reload_mode(&config_params,
DMA_CH_SRCRELOAD_BURST_gc);
dma_channel_set_src_dir_mode(&config_params,
DMA_CH_SRCDIR_FIXED_gc);
dma_channel_set_dest_reload_mode(&config_params,
DMA_CH_DESTRELOAD_NONE_gc);
dma_channel_set_dest_dir_mode(&config_params,
DMA_CH_DESTDIR_INC_gc);
/* Set trigger source to TCC0's overflow */
dma_channel_set_trigger_source(&config_params,
DMA_CH_TRIGSRC_TCC0_OVF_gc);
/* Transfer DEST_BLOCK_TC_SIZE bytes */
dma_channel_set_transfer_count(&config_params,
DEST_BLOCK_TC_SIZE);
/* Set address */
dma_channel_set_source_address(&config_params,
(uint16_t)(uintptr_t)&timer_overflow_counter);
dma_channel_set_destination_address(&config_params,
(uint16_t)(uintptr_t)dest_block_tc);
/* Reset the channel */
dma_channel_reset(DMA_CHANNEL_0);
/* Write the config */
dma_channel_write_config(DMA_CHANNEL_0, &config_params);
/* Enable the channel */
dma_channel_enable(DMA_CHANNEL_0);
/* Wait for transfer to finish */
while (!dma_has_completed) {
/* Intentionally left empty */
}
/* Disable DMA */
dma_disable();
/* Verify that the result is as expected */
success = block_compare(dest_block_tc,
expected_result_tc, DEST_BLOCK_TC_SIZE);
test_assert_true(test, success, "Result is not as expected");
}
