int disp_al_lcd_cfg(u32 screen_id, disp_panel_para * panel, panel_extend_para *extend_panel)
{
struct lcd_clk_info info;
al_priv.output_type[screen_id] = (u32)DISP_OUTPUT_TYPE_LCD;
al_priv.output_type[screen_id] = (u32)panel->lcd_if;
tcon_init(screen_id);
disp_al_lcd_get_clk_info(screen_id, &info, panel);
tcon0_set_dclk_div(screen_id, info.tcon_div);
if(0 != tcon0_cfg(screen_id, panel))
DE_WRN("lcd cfg fail!\n");
else
DE_INF("lcd cfg ok!\n");
tcon0_cfg_ext(screen_id, extend_panel);
if(LCD_IF_DSI == panel->lcd_if) {
#if defined(SUPPORT_DSI)
if(0 != dsi_cfg(screen_id, panel)) {
DE_WRN("dsi cfg fail!\n");
}
#endif
}
return 0;
}
/*
*********************************************************************************************************
* disp_clk_cfg
*
* Description : Config PLL and mclk depend on all kinds of display devices
*
* Arguments : screen_id <display channel>
* type <display device type: tv/vga/hdmi/lcd>
* mode <display mode of tv/vga/hdmi: 480i, ntsc...>
*
* Returns : success <DIS_SUCCESS>
* fail <DIS_FAIL>
*
* Note : None.
*
*********************************************************************************************************
*/
__s32 disp_clk_cfg(__u32 screen_id, __u32 type, __u8 mode)
{
__u32 pll_freq = 297000000, tve_freq = 27000000;
__u32 hdmi_freq = 74250000;
__s32 videopll_sel, pre_scale = 1;
__u32 lcd_clk_div = 0;
__u32 pll_2x = 0;
if(type == DISP_OUTPUT_TYPE_TV || type == DISP_OUTPUT_TYPE_HDMI) {
pll_freq = clk_tab.tv_clk_tab[mode].pll_clk;
tve_freq = clk_tab.tv_clk_tab[mode].tve_clk;
pre_scale = clk_tab.tv_clk_tab[mode].pre_scale;
hdmi_freq = clk_tab.tv_clk_tab[mode].hdmi_clk;
pll_2x = clk_tab.tv_clk_tab[mode].pll_2x;
} else if(type == DISP_OUTPUT_TYPE_VGA) {
pll_freq = clk_tab.vga_clk_tab[mode].pll_clk;
tve_freq = clk_tab.vga_clk_tab[mode].tve_clk;
pre_scale = clk_tab.vga_clk_tab[mode].pre_scale;
pll_2x = clk_tab.vga_clk_tab[mode].pll_2x;
} else if(type == DISP_OUTPUT_TYPE_LCD) {
pll_freq = LCD_PLL_Calc(screen_id, (__panel_para_t*)&gpanel_info[screen_id], &lcd_clk_div);
pre_scale = 1;
#if (!defined CONFIG_ARCH_SUN7I)
__disp_ccmu_coef coef;
#if defined (CONFIG_A50_FPGA)
if(gpanel_info[screen_id].lcd_if != LCD_IF_LVDS) {
lcd_clk_div = 3;
}
#endif
tcon0_set_dclk_div(screen_id,lcd_clk_div);
disp_mipipll_calc_coefficient(297000000, pll_freq, &coef);
disp_mipipll_set_coefficient(&coef);
return DIS_SUCCESS;
#endif
} else {
return DIS_SUCCESS;
}
if ( (videopll_sel = disp_pll_assign(screen_id, pll_freq)) == -1) {
DE_WRN("===pll assign fail====\n");
return DIS_FAIL;
}
disp_pll_set(screen_id, videopll_sel, pll_freq, tve_freq, pre_scale, lcd_clk_div, hdmi_freq, pll_2x, type);
if(videopll_sel == 0) {
gdisp.screen[screen_id].pll_use_status |= VIDEO_PLL0_USED;
} else if(videopll_sel == 1) {
gdisp.screen[screen_id].pll_use_status |= VIDEO_PLL1_USED;
}
return DIS_SUCCESS;
}
int disp_al_vdevice_cfg(u32 screen_id, disp_video_timings *video_info, disp_vdevice_interface_para *para)
{
struct lcd_clk_info clk_info;
disp_panel_para info;
al_priv.output_type[screen_id] = (u32)DISP_OUTPUT_TYPE_LCD;
al_priv.output_mode[screen_id] = (u32)para->intf;
memset(&info, 0, sizeof(disp_panel_para));
info.lcd_if = para->intf;
info.lcd_x = video_info->x_res;
info.lcd_y = video_info->y_res;
info.lcd_hv_if = (disp_lcd_hv_if)para->sub_intf;
info.lcd_dclk_freq = video_info->pixel_clk;
info.lcd_ht = video_info->hor_total_time;
info.lcd_hbp = video_info->hor_back_porch + video_info->hor_sync_time;
info.lcd_hspw = video_info->hor_sync_time;
info.lcd_vt = video_info->ver_total_time;
info.lcd_vbp = video_info->ver_back_porch + video_info->ver_sync_time;
info.lcd_vspw = video_info->ver_sync_time;
info.lcd_hv_syuv_fdly = para->fdelay;
if(LCD_HV_IF_CCIR656_2CYC == info.lcd_hv_if)
info.lcd_hv_syuv_seq = para->sequence;
else
info.lcd_hv_srgb_seq = para->sequence;
tcon_init(screen_id);
disp_al_lcd_get_clk_info(screen_id, &clk_info, &info);
clk_info.tcon_div = 11;//fixme
tcon0_set_dclk_div(screen_id, clk_info.tcon_div);
if(0 != tcon0_cfg(screen_id, &info))
DE_WRN("lcd cfg fail!\n");
else
DE_INF("lcd cfg ok!\n");
return 0;
}
int disp_al_lcd_cfg(u32 screen_id, disp_panel_para * panel)
{
struct lcd_clk_info info;
tcon_init(screen_id);
disp_al_lcd_get_clk_info(screen_id, &info, panel);
DE_INF("lcd %d clk_div=%d!\n", screen_id, info.tcon_div);
tcon0_set_dclk_div(screen_id, info.tcon_div);
if(0 != tcon0_cfg(screen_id, panel))
DE_WRN("lcd cfg fail!\n");
else
DE_INF("lcd cfg ok!\n");
if(LCD_IF_DSI == panel->lcd_if) {
#if defined(SUPPORT_DSI)
if(0 != dsi_cfg(screen_id, panel)) {
DE_WRN("dsi cfg fail!\n");
}
#endif
}
return 0;
}
static __s32 disp_pll_set(__u32 screen_id, __s32 videopll_sel, __u32 pll_freq, __u32 tve_freq, __s32 pre_scale,
__u32 lcd_clk_div, __u32 hdmi_freq, __u32 pll_2x, __u32 type)
{
__u32 videopll;
__hdle h_lcdmclk0, h_lcdmclk1;
__s32 pll_2x_req;
__u32 lcdmclk1_div, hdmiclk_div;
if(type == DISP_OUTPUT_TYPE_LCD) {
/* mipi pll */
if(videopll_sel == 2) {
videopll = SYS_CLK_MIPIPLL;
//pll_freq = ((pll_freq + 12000000)/ 24000000) * 24000000;
//OSAL_CCMU_SetSrcFreq(AW_SYS_CLK_PLL6, pll_freq);
}
/* video pll0 or video pll1 */
else {
pll_2x_req = (pll_freq>600000000)?1:0;
if(pll_2x_req) {
pll_freq /= 2;
}
//in 3M unit
pll_freq = (pll_freq + 1500000)/3000000;
pll_freq = pll_freq * 3000000;
videopll = (videopll_sel == 0)?SYS_CLK_PLL3:SYS_CLK_PLL7;
OSAL_CCMU_SetSrcFreq(videopll,pll_freq);
if(pll_2x_req) {
videopll = (videopll == SYS_CLK_PLL3)?SYS_CLK_PLL3X2:SYS_CLK_PLL7X2;
}
}
if(gpanel_info[screen_id].tcon_index == 0) {
h_lcdmclk0 = (screen_id == 0)?h_lcd0ch0mclk0 : h_lcd1ch0mclk0;
OSAL_CCMU_SetMclkSrc(h_lcdmclk0, videopll);
tcon0_set_dclk_div(screen_id,lcd_clk_div);
/* todo? --dphy clk fix to 297/2M */
if(gpanel_info[screen_id].lcd_if == LCD_IF_DSI) {
OSAL_CCMU_SetMclkSrc(h_dsimclk_s, videopll);
OSAL_CCMU_SetMclkDiv(h_dsimclk_s, 1);
OSAL_CCMU_SetMclkSrc(h_dsimclk_p, SYS_CLK_PLL7);
OSAL_CCMU_SetMclkDiv(h_dsimclk_p, 1);
}
}
else {
h_lcdmclk1 = (screen_id == 0)?h_lcd0ch1mclk1 : h_lcd1ch1mclk1;
OSAL_CCMU_SetMclkSrc(h_lcdmclk1, videopll);
OSAL_CCMU_SetMclkDiv(h_lcdmclk1, lcd_clk_div);
}
}
/* tv/vga/hdmi */
else {
__u32 pll_freq_used;
pll_2x_req = pll_2x;
videopll = (videopll_sel == 0)?SYS_CLK_PLL3:SYS_CLK_PLL7;
OSAL_CCMU_SetSrcFreq(videopll,pll_freq); //Set related Video Pll Frequency
videopll = (videopll_sel == 0)?
((pll_2x_req)?SYS_CLK_PLL3X2: SYS_CLK_PLL3):
((pll_2x_req)?SYS_CLK_PLL7X2: SYS_CLK_PLL7);
pll_freq_used = pll_freq * (pll_2x_req + 1);
lcdmclk1_div = (pll_freq_used + (tve_freq / 2)) / tve_freq;
hdmiclk_div = (pll_freq_used + (hdmi_freq / 2)) / hdmi_freq;
h_lcdmclk1 = (screen_id == 0)?h_lcd0ch1mclk1 : h_lcd1ch1mclk1;
OSAL_CCMU_SetMclkSrc(h_lcdmclk1, videopll);
OSAL_CCMU_SetMclkDiv(h_lcdmclk1, lcdmclk1_div);
/* hdmi internal mode */
if(type == DISP_OUTPUT_TYPE_HDMI && gdisp.screen[screen_id].hdmi_index == 0) {
OSAL_CCMU_SetMclkSrc(h_hdmimclk, videopll);
OSAL_CCMU_SetMclkDiv(h_hdmimclk, hdmiclk_div);
if(gdisp.init_para.hdmi_set_pll != NULL) {
if((videopll == SYS_CLK_PLL3X2) || (videopll == SYS_CLK_PLL3)) {
gdisp.init_para.hdmi_set_pll(0, pll_freq);
} else {
gdisp.init_para.hdmi_set_pll(1, pll_freq);
}
} else {
DE_WRN("gdisp.init_para.hdmi_set_pll is NULL\n");
}
}
}
return DIS_SUCCESS;
}