void __init tegra_cpu_reset_handler_init(void) { #ifdef CONFIG_SMP __tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] = *((u32 *)cpu_present_mask); __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] = virt_to_phys((void *)tegra_secondary_startup); #endif #ifdef CONFIG_PM_SLEEP __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP1] = TEGRA_IRAM_CODE_AREA; __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] = virt_to_phys((void *)tegra_resume); #endif /* Push all of reset handler data out to the L3 memory system. */ __cpuc_coherent_kern_range( (unsigned long)&__tegra_cpu_reset_handler_data[0], (unsigned long)&__tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE]); outer_clean_range(__pa(&__tegra_cpu_reset_handler_data[0]), __pa(&__tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE])); tegra_cpu_reset_handler_enable(); }
void tegra_cpu_reset_handler_restore(void) { unsigned int i; BUG_ON(is_enabled); tegra_cpu_reset_handler_enable(); for (i = 0; i < TEGRA_RESET_DATA_SIZE; i++) tegra_cpu_reset_handler_ptr[i] = __tegra_cpu_reset_handler_data[i]; is_enabled = true; }
void __init tegra_cpu_reset_handler_init(void) { #ifdef CONFIG_SMP __tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] = *((u32 *)cpu_present_mask); __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] = virt_to_phys((void *)tegra_secondary_startup); #endif tegra_cpu_reset_handler_enable(); }
void __init tegra_cpu_reset_handler_init(void) { #ifdef CONFIG_SMP __tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] = *((u32 *)cpu_possible_mask); __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] = virt_to_phys((void *)tegra_secondary_startup); #endif #ifdef CONFIG_PM_SLEEP __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP1] = TEGRA_IRAM_CODE_AREA; __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] = virt_to_phys((void *)tegra_resume); #endif tegra_cpu_reset_handler_enable(); }