int __init dra7xx_dt_clk_init(void)
{
int rc;
struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck;
ti_dt_clocks_register(dra7xx_clks);
omap2_clk_disable_autoidle_all();
abe_dpll_mux = clk_get_sys(NULL, "abe_dpll_sys_clk_mux");
sys_clkin2 = clk_get_sys(NULL, "sys_clkin2");
dpll_ck = clk_get_sys(NULL, "dpll_abe_ck");
rc = clk_set_parent(abe_dpll_mux, sys_clkin2);
if (!rc)
rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ);
if (rc)
pr_err("%s: failed to configure ABE DPLL!\n", __func__);
dpll_ck = clk_get_sys(NULL, "dpll_abe_m2x2_ck");
rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ * 2);
if (rc)
pr_err("%s: failed to configure ABE DPLL m2x2!\n", __func__);
dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
if (rc)
pr_err("%s: failed to configure GMAC DPLL!\n", __func__);
return rc;
}
int __init omap5xxx_dt_clk_init(void)
{
int rc;
struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
struct clk *iva_dpll, *iva_h11x2_dpll, *iva_h12x2_dpll;
ti_dt_clocks_register(omap54xx_clks);
omap2_clk_disable_autoidle_all();
abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux");
sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
if (!rc)
rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ);
if (rc)
pr_err("%s: failed to configure ABE DPLL!\n", __func__);
abe_dpll = clk_get_sys(NULL, "dpll_abe_m2x2_ck");
if (!rc)
rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ * 2);
if (rc)
pr_err("%s: failed to configure ABE m2x2 DPLL!\n", __func__);
usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ);
if (rc)
pr_err("%s: failed to configure USB DPLL!\n", __func__);
usb_dpll = clk_get_sys(NULL, "dpll_usb_m2_ck");
rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ/2);
if (rc)
pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
/*
* Lock the IVA DPLL and its derivative clocks so that the DSP and
* IVA processors are running at nominal operating points rather
* than at a bypass clock rate or at a misconfigured output rate.
*/
iva_dpll = clk_get_sys(NULL, "dpll_iva_ck");
rc = clk_set_rate(iva_dpll, OMAP5_DPLL_IVA_DEFFREQ);
if (!rc) {
iva_h11x2_dpll = clk_get_sys(NULL, "dpll_iva_h11x2_ck");
rc = clk_set_rate(iva_h11x2_dpll, OMAP5_DSP_GCLK_NOMFREQ);
if (rc)
pr_err("%s: failed to configure IVA DPLL h11x2 divider!\n",
__func__);
iva_h12x2_dpll = clk_get_sys(NULL, "dpll_iva_h12x2_ck");
rc = clk_set_rate(iva_h12x2_dpll, OMAP5_IVA_GCLK_NOMFREQ);
if (rc)
pr_err("%s: failed to configure IVA DPLL h12x2 divider!\n",
__func__);
} else {
pr_err("%s: failed to configure IVA DPLL!\n", __func__);
}
return 0;
}
int __init omap4xxx_dt_clk_init(void)
{
int rc;
struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
ti_dt_clocks_register(omap44xx_clks);
omap2_clk_disable_autoidle_all();
/*
* Lock USB DPLL on OMAP4 devices so that the L3INIT power
* domain can transition to retention state when not in use.
*/
usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ);
if (rc)
pr_err("%s: failed to configure USB DPLL!\n", __func__);
/*
* On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
* state when turning the ABE clock domain. Workaround this by
* locking the ABE DPLL on boot.
* Lock the ABE DPLL in any case to avoid issues with audio.
*/
abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck");
sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
if (!rc)
rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ);
if (rc)
pr_err("%s: failed to configure ABE DPLL!\n", __func__);
return 0;
}
int __init omap5xxx_dt_clk_init(void)
{
int rc;
struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
ti_dt_clocks_register(omap54xx_clks);
omap2_clk_disable_autoidle_all();
abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux");
sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
if (!rc)
rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ);
if (rc)
pr_err("%s: failed to configure ABE DPLL!\n", __func__);
usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ);
if (rc)
pr_err("%s: failed to configure USB DPLL!\n", __func__);
usb_dpll = clk_get_sys(NULL, "dpll_usb_m2_ck");
rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ/2);
if (rc)
pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
return 0;
}
int __init dm816x_dt_clk_init(void)
{
ti_dt_clocks_register(dm816x_clks);
omap2_clk_disable_autoidle_all();
omap2_clk_enable_init_clocks(enable_init_clks,
ARRAY_SIZE(enable_init_clks));
return 0;
}
static int __init omap3xxx_dt_clk_init(int soc_type)
{
if (soc_type == OMAP3_SOC_AM35XX || soc_type == OMAP3_SOC_OMAP3630 ||
soc_type == OMAP3_SOC_OMAP3430_ES1 ||
soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS)
ti_dt_clocks_register(omap3xxx_clks);
if (soc_type == OMAP3_SOC_AM35XX)
ti_dt_clocks_register(am35xx_clks);
if (soc_type == OMAP3_SOC_OMAP3630 || soc_type == OMAP3_SOC_AM35XX ||
soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS)
ti_dt_clocks_register(omap36xx_am35xx_omap3430es2plus_clks);
if (soc_type == OMAP3_SOC_OMAP3430_ES1)
ti_dt_clocks_register(omap3430es1_clks);
if (soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS ||
soc_type == OMAP3_SOC_OMAP3630)
ti_dt_clocks_register(omap36xx_omap3430es2plus_clks);
omap2_clk_disable_autoidle_all();
ti_clk_add_aliases();
omap2_clk_enable_init_clocks(enable_init_clks,
ARRAY_SIZE(enable_init_clks));
pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
(clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 1000000),
(clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 100000) % 10,
(clk_get_rate(clk_get_sys(NULL, "core_ck")) / 1000000),
(clk_get_rate(clk_get_sys(NULL, "arm_fck")) / 1000000));
if (soc_type != OMAP3_SOC_OMAP3430_ES1)
omap3_clk_lock_dpll5();
return 0;
}
static int __init omap2xxx_dt_clk_init(int soc_type)
{
ti_dt_clocks_register(omap2xxx_clks);
if (soc_type == OMAP2_SOC_OMAP2420)
ti_dt_clocks_register(omap2420_clks);
else
ti_dt_clocks_register(omap2430_clks);
omap2xxx_clkt_vps_init();
omap2_clk_disable_autoidle_all();
omap2_clk_enable_init_clocks(enable_init_clks,
ARRAY_SIZE(enable_init_clks));
pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
(clk_get_rate(clk_get_sys(NULL, "sys_ck")) / 1000000),
(clk_get_rate(clk_get_sys(NULL, "sys_ck")) / 100000) % 10,
(clk_get_rate(clk_get_sys(NULL, "dpll_ck")) / 1000000),
(clk_get_rate(clk_get_sys(NULL, "mpu_ck")) / 1000000));
return 0;
}
int __init am33xx_dt_clk_init(void)
{
struct clk *clk1, *clk2;
ti_dt_clocks_register(am33xx_clks);
omap2_clk_disable_autoidle_all();
ti_clk_add_aliases();
omap2_clk_enable_init_clocks(enable_init_clks,
ARRAY_SIZE(enable_init_clks));
/* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
* physically present, in such a case HWMOD enabling of
* clock would be failure with default parent. And timer
* probe thinks clock is already enabled, this leads to
* crash upon accessing timer 3 & 6 registers in probe.
* Fix by setting parent of both these timers to master
* oscillator clock.
*/
clk1 = clk_get_sys(NULL, "sys_clkin_ck");
clk2 = clk_get_sys(NULL, "timer3_fck");
clk_set_parent(clk2, clk1);
clk2 = clk_get_sys(NULL, "timer6_fck");
clk_set_parent(clk2, clk1);
/*
* The On-Chip 32K RC Osc clock is not an accurate clock-source as per
* the design/spec, so as a result, for example, timer which supposed
* to get expired @60Sec, but will expire somewhere ~@40Sec, which is
* not expected by any use-case, so change WDT1 clock source to PRCM
* 32KHz clock.
*/
clk1 = clk_get_sys(NULL, "wdt1_fck");
clk2 = clk_get_sys(NULL, "clkdiv32k_ick");
clk_set_parent(clk1, clk2);
return 0;
}
int __init dra7xx_dt_clk_init(void)
{
int rc;
struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck, *dss_deshdcp_ck;
struct clk *ipu1_gfclk, *ipu1_gfclk_parent;
struct clk *dsp_dpll, *dsp_m2_dpll, *dsp_m3x2_dpll;
struct clk *atl_fck, *atl_parent;
ti_dt_clocks_register(dra7xx_clks);
omap2_clk_disable_autoidle_all();
abe_dpll_mux = clk_get_sys(NULL, "abe_dpll_sys_clk_mux");
sys_clkin2 = clk_get_sys(NULL, "sys_clkin2");
dpll_ck = clk_get_sys(NULL, "dpll_abe_ck");
rc = clk_set_parent(abe_dpll_mux, sys_clkin2);
if (!rc)
rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ);
if (rc)
pr_err("%s: failed to configure ABE DPLL!\n", __func__);
dpll_ck = clk_get_sys(NULL, "dpll_abe_m2x2_ck");
rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ * 2);
if (rc)
pr_err("%s: failed to configure ABE DPLL m2x2!\n", __func__);
dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
if (rc)
pr_err("%s: failed to configure GMAC DPLL!\n", __func__);
dss_deshdcp_ck = clk_get_sys(NULL, "dss_deshdcp_clk");
rc = clk_prepare_enable(dss_deshdcp_ck);
if (rc)
pr_err("%s: failed to enable DESHDCP clock\n", __func__);
ipu1_gfclk = clk_get_sys(NULL, "ipu1_gfclk_mux");
ipu1_gfclk_parent = clk_get_sys(NULL, "dpll_core_h22x2_ck");
rc = clk_set_parent(ipu1_gfclk, ipu1_gfclk_parent);
if (rc)
pr_err("%s: failed to reparent ipu1_gfclk_mux\n", __func__);
dsp_dpll = clk_get_sys(NULL, "dpll_dsp_ck");
rc = clk_set_rate(dsp_dpll, DRA7_DPLL_DSP_DEFFREQ);
if (!rc) {
dsp_m2_dpll = clk_get_sys(NULL, "dpll_dsp_m2_ck");
rc = clk_set_rate(dsp_m2_dpll, DRA7_DPLL_DSP_GFCLK_NOMFREQ);
if (rc)
pr_err("%s: failed to configure DSP DPLL m2 output!\n",
__func__);
dsp_m3x2_dpll = clk_get_sys(NULL, "dpll_dsp_m3x2_ck");
rc = clk_set_rate(dsp_m3x2_dpll, DRA7_DPLL_EVE_GCLK_NOMFREQ);
if (rc)
pr_err("%s: failed to configure DSP DPLL m3x2 divider!\n",
__func__);
} else {
pr_err("%s: failed to configure DSP DPLL!\n", __func__);
}
atl_fck = clk_get_sys(NULL, "atl_gfclk_mux");
atl_parent = clk_get_sys(NULL, "dpll_abe_m2_ck");
rc = clk_set_parent(atl_fck, atl_parent);
if (rc)
pr_err("%s: failed to reparent atl_gfclk_mux\n", __func__);
atl_fck = clk_get_sys(NULL, "atl_clkin2_ck");
rc = clk_set_rate(atl_fck, DRA7_ATL_DEFFREQ);
if (rc)
pr_err("%s: failed to set atl_clkin2_ck\n", __func__);
atl_fck = clk_get_sys(NULL, "atl_clkin1_ck");
rc = clk_set_rate(atl_fck, DRA7_ATL_DEFFREQ);
if (rc)
pr_err("%s: failed to set atl_clkin1_ck\n", __func__);
dpll_ck = clk_get_sys(NULL, "dpll_usb_ck");
rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ);
if (rc)
pr_err("%s: failed to configure USB DPLL!\n", __func__);
dpll_ck = clk_get_sys(NULL, "dpll_usb_m2_ck");
rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2);
if (rc)
pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
return rc;
}
