static int64_t opb_write(struct proc_chip *chip, uint32_t addr, uint32_t data,
uint32_t sz)
{
uint64_t ctl = ECCB_CTL_MAGIC, stat;
int64_t rc, tout;
uint64_t data_reg;
switch(sz) {
case 1:
data_reg = ((uint64_t)data) << 56;
break;
case 2:
data_reg = ((uint64_t)data) << 48;
break;
case 4:
data_reg = ((uint64_t)data) << 32;
break;
default:
prerror("LPC: Invalid data size %d\n", sz);
return OPAL_PARAMETER;
}
rc = xscom_write(chip->id, chip->lpc_xbase + ECCB_DATA, data_reg);
if (rc) {
log_simple_error(&e_info(OPAL_RC_LPC_WRITE),
"LPC: XSCOM write to ECCB DATA error %lld\n", rc);
return rc;
}
ctl = SETFIELD(ECCB_CTL_DATASZ, ctl, sz);
ctl = SETFIELD(ECCB_CTL_ADDRLEN, ctl, ECCB_ADDRLEN_4B);
ctl = SETFIELD(ECCB_CTL_ADDR, ctl, addr);
rc = xscom_write(chip->id, chip->lpc_xbase + ECCB_CTL, ctl);
if (rc) {
log_simple_error(&e_info(OPAL_RC_LPC_WRITE),
"LPC: XSCOM write to ECCB CTL error %lld\n", rc);
return rc;
}
for (tout = 0; tout < ECCB_TIMEOUT; tout++) {
rc = xscom_read(chip->id, chip->lpc_xbase + ECCB_STAT, &stat);
if (rc) {
log_simple_error(&e_info(OPAL_RC_LPC_WRITE),
"LPC: XSCOM read from ECCB STAT err %lld\n",
rc);
return rc;
}
if (stat & ECCB_STAT_OP_DONE) {
if (stat & ECCB_STAT_ERR_MASK) {
log_simple_error(&e_info(OPAL_RC_LPC_WRITE),
"LPC: Error status: 0x%llx\n", stat);
return OPAL_HARDWARE;
}
return OPAL_SUCCESS;
}
time_wait_nopoll(100);
}
log_simple_error(&e_info(OPAL_RC_LPC_WRITE), "LPC: Write timeout !\n");
return OPAL_HARDWARE;
}
static int64_t opb_read(struct lpcm *lpc, uint32_t addr, uint32_t *data,
uint32_t sz)
{
uint64_t ctl = ECCB_CTL_MAGIC | ECCB_CTL_READ, stat;
int64_t rc, tout;
if (lpc->mbase)
return opb_mmio_read(lpc, addr, data, sz);
if (sz != 1 && sz != 2 && sz != 4) {
prerror("Invalid data size %d\n", sz);
return OPAL_PARAMETER;
}
ctl = SETFIELD(ECCB_CTL_DATASZ, ctl, sz);
ctl = SETFIELD(ECCB_CTL_ADDRLEN, ctl, ECCB_ADDRLEN_4B);
ctl = SETFIELD(ECCB_CTL_ADDR, ctl, addr);
rc = xscom_write(lpc->chip_id, lpc->xbase + ECCB_CTL, ctl);
if (rc) {
log_simple_error(&e_info(OPAL_RC_LPC_READ),
"LPC: XSCOM write to ECCB CTL error %lld\n", rc);
return rc;
}
for (tout = 0; tout < ECCB_TIMEOUT; tout++) {
rc = xscom_read(lpc->chip_id, lpc->xbase + ECCB_STAT,
&stat);
if (rc) {
log_simple_error(&e_info(OPAL_RC_LPC_READ),
"LPC: XSCOM read from ECCB STAT err %lld\n",
rc);
return rc;
}
if (stat & ECCB_STAT_OP_DONE) {
uint32_t rdata = GETFIELD(ECCB_STAT_RD_DATA, stat);
if (stat & ECCB_STAT_ERR_MASK) {
log_simple_error(&e_info(OPAL_RC_LPC_READ),
"LPC: Error status: 0x%llx\n", stat);
return OPAL_HARDWARE;
}
switch(sz) {
case 1:
*data = rdata >> 24;
break;
case 2:
*data = rdata >> 16;
break;
default:
*data = rdata;
break;
}
return 0;
}
time_wait_nopoll(100);
}
