void TIM2_init() {
uint32_t SystemCoreClock = 72000000;
uint16_t prescalerValue = (uint16_t) (SystemCoreClock / 24000000) - 1;
rcc_clk_enable(RCC_TIMER2);
/* Time base configuration */
timer_pause(TIMER2);
timer_set_prescaler(TIMER2, prescalerValue);
timer_set_reload(TIMER2, 29); // 800kHz
/* Timing Mode configuration: Channel 1 */
timer_set_mode(TIMER2, 1, TIMER_OUTPUT_COMPARE);
timer_set_compare(TIMER2, 1, 8);
timer_oc_set_mode(TIMER2, 1, TIMER_OC_MODE_FROZEN, ~TIMER_OC_PE);
/* Timing Mode configuration: Channel 2 */
timer_set_mode(TIMER2, 2, TIMER_OUTPUT_COMPARE);
timer_set_compare(TIMER2, 2, 17);
timer_oc_set_mode(TIMER2, 2, TIMER_OC_MODE_PWM_1, ~TIMER_OC_PE);
//timer_resume(TIMER2);
timer_attach_interrupt(TIMER2, TIMER_UPDATE_INTERRUPT, TIM2_IRQHandler);
/* configure TIM2 interrupt */
nvic_irq_set_priority(NVIC_TIMER2, 2);
nvic_irq_enable(NVIC_TIMER2);
}
static void timer_default_config(timer_dev *dev) {
timer_adv_reg_map *regs = (dev->regs).adv;
const uint16 full_overflow = 0xFFFF;
const uint16 half_duty = 0x8FFF;
timer_init(dev);
timer_pause(dev);
regs->CR1 = TIMER_CR1_ARPE;
regs->PSC = 1;
regs->SR = 0;
regs->DIER = 0;
regs->EGR = TIMER_EGR_UG;
switch (dev->type) {
case TIMER_ADVANCED:
regs->BDTR = TIMER_BDTR_MOE | TIMER_BDTR_LOCK_OFF;
// fall-through
case TIMER_GENERAL:
timer_set_reload(dev, full_overflow);
for (uint8 channel = 1; channel <= 4; channel++) {
if (timer_has_cc_channel(dev, channel)) {
timer_set_compare(dev, channel, half_duty);
timer_oc_set_mode(dev, channel, TIMER_OC_MODE_PWM_1,
TIMER_OC_PE);
}
}
// fall-through
case TIMER_BASIC:
break;
}
timer_generate_update(dev);
timer_resume(dev);
}
static void output_compare_mode(timer_dev *dev, uint8 channel) {
timer_oc_set_mode(dev, channel, TIMER_OC_MODE_ACTIVE_ON_MATCH, 0);
timer_cc_enable(dev, channel);
}
static void pwm_mode(timer_dev *dev, uint8 channel) {
timer_disable_irq(dev, channel);
timer_oc_set_mode(dev, channel, TIMER_OC_MODE_PWM_1, TIMER_OC_PE);
timer_cc_enable(dev, channel);
}
