static void
timer_jazzio_attach(device_t parent, device_t self, void *aux)
{
if (timer_jazzio_conf == NULL)
panic("timer_jazzio_conf isn't initialized");
aprint_normal("\n");
evcnt_attach_static(&timer_jazzio_ev);
(*platform->set_intr)(timer_jazzio_conf->tjc_intr_mask,
timer_jazzio_conf->tjc_intr, ARC_INTPRI_TIMER_INT);
timerattach(self, &timerfns_jazzio);
timer_jazzio_found = 1;
}
void
timerattach_obio_4(struct device *parent, struct device *self, void *aux)
{
union obio_attach_args *uoba = aux;
struct obio4_attach_args *oba = &uoba->uoba_oba4;
bus_space_handle_t bh;
if (bus_space_map2(oba->oba_bustag,
oba->oba_paddr,
sizeof(struct timerreg_4),
BUS_SPACE_MAP_LINEAR,
TIMERREG_VA,
&bh) != 0) {
printf(": can't map registers\n");
return;
}
timerattach(&timerreg4->t_c10.t_counter, &timerreg4->t_c10.t_limit);
}
void
timerattach_mainbus_4c(struct device *parent, struct device *self, void *aux)
{
struct mainbus_attach_args *ma = aux;
bus_space_handle_t bh;
/*
* This time we ignore any existing virtual address because
* we have a fixed virtual address for the timer, to make
* microtime() faster.
*/
if (bus_space_map2(ma->ma_bustag,
ma->ma_paddr,
sizeof(struct timerreg_4),
BUS_SPACE_MAP_LINEAR,
TIMERREG_VA, &bh) != 0) {
printf(": can't map registers\n");
return;
}
timerattach(&timerreg4->t_c10.t_counter, &timerreg4->t_c10.t_limit);
}
void
timerattach_obio_4m(device_t parent, device_t self, void *aux)
{
union obio_attach_args *uoba = aux;
struct sbus_attach_args *sa = &uoba->uoba_sbus;
struct cpu_info *cpi;
bus_space_handle_t bh;
int i;
CPU_INFO_ITERATOR n;
if (sa->sa_nreg < 2) {
printf(": only %d register sets\n", sa->sa_nreg);
return;
}
/* Map the system timer */
i = sa->sa_nreg - 1;
if (bus_space_map2(sa->sa_bustag,
BUS_ADDR(sa->sa_reg[i].oa_space,
sa->sa_reg[i].oa_base),
sizeof(struct timer_4m),
BUS_SPACE_MAP_LINEAR,
TIMERREG_VA, &bh) != 0) {
printf(": can't map registers\n");
return;
}
timerreg4m = (struct timer_4m *)TIMERREG_VA;
/* Map each CPU's counter */
for (i = 0; i < sa->sa_nreg - 1; i++) {
/*
* Check whether the CPU corresponding to this timer
* register is installed.
*/
for (CPU_INFO_FOREACH(n, cpi)) {
if ((i == 0 && sparc_ncpus == 1) || cpi->mid == i + 8) {
/* We got a corresponding MID. */
break;
}
cpi = NULL;
}
if (cpi == NULL)
continue;
if (sbus_bus_map(sa->sa_bustag,
sa->sa_reg[i].oa_space,
sa->sa_reg[i].oa_base,
sizeof(struct timer_4m),
BUS_SPACE_MAP_LINEAR,
&bh) != 0) {
printf(": can't map CPU counter %d\n", i);
return;
}
cpi->counterreg_4m = (struct counter_4m *)bh;
}
#if defined(MULTIPROCESSOR)
if (sparc_ncpus > 1) {
/*
* Note that we don't actually use this cookie after checking
* it was establised, we call directly via raise_ipi() on
* IPL_HARDCLOCK.
*/
void *hardclock_cookie;
hardclock_cookie = sparc_softintr_establish(IPL_HARDCLOCK,
hardclock_ipi, NULL);
if (hardclock_cookie == NULL)
panic("timerattach: cannot establish hardclock_intr");
}
#endif
/* Put processor counter in "timer" mode */
timerreg4m->t_cfg = 0;
timerattach(&timerreg4m->t_counter, &timerreg4m->t_limit);
}
