static long alpha_pll_round_rate(struct clk *c, unsigned long rate)
{
struct alpha_pll_clk *pll = to_alpha_pll_clk(c);
struct alpha_pll_vco_tbl *v = pll->vco_tbl;
int ret;
u32 l_val;
unsigned long freq_hz;
u64 a_val;
int i;
if (pll->no_prepared_reconfig && c->prepare_count)
return -EINVAL;
freq_hz = round_rate_up(pll, rate, &l_val, &a_val);
if (rate < pll->min_supported_freq)
return pll->min_supported_freq;
if (pll->is_fabia)
return freq_hz;
ret = find_vco(pll, freq_hz);
if (!IS_ERR_VALUE(ret))
return freq_hz;
freq_hz = 0;
for (i = 0; i < pll->num_vco; i++) {
if (is_better_rate(rate, freq_hz, v[i].min_freq))
freq_hz = v[i].min_freq;
if (is_better_rate(rate, freq_hz, v[i].max_freq))
freq_hz = v[i].max_freq;
}
if (!freq_hz)
return -EINVAL;
return freq_hz;
}
static int fabia_alpha_pll_set_rate(struct clk *c, unsigned long rate)
{
struct alpha_pll_clk *pll = to_alpha_pll_clk(c);
unsigned long flags, freq_hz;
u32 l_val;
u64 a_val;
freq_hz = round_rate_up(pll, rate, &l_val, &a_val);
if (freq_hz > rate + FABIA_RATE_MARGIN || freq_hz < rate) {
pr_err("%s: Call clk_set_rate with rounded rates!\n",
c->dbg_name);
return -EINVAL;
}
spin_lock_irqsave(&c->lock, flags);
/* Set the new L value */
writel_relaxed(l_val, FABIA_L_REG(pll));
if (pll->fabia_frac_offset)
writel_relaxed(a_val, FABIA_FRAC_OFF(pll));
else
writel_relaxed(a_val, FABIA_FRAC_REG(pll));
alpha_pll_dynamic_update(pll);
spin_unlock_irqrestore(&c->lock, flags);
return 0;
}
static enum handoff alpha_pll_handoff(struct clk *c)
{
struct alpha_pll_clk *pll = to_alpha_pll_clk(c);
struct alpha_pll_masks *masks = pll->masks;
u64 a_val;
u32 alpha_en, l_val, regval;
/* Set the PLL_HW_UPDATE_LOGIC_BYPASS bit before continuing */
if (pll->dynamic_update) {
regval = readl_relaxed(MODE_REG(pll));
regval |= ALPHA_PLL_HW_UPDATE_LOGIC_BYPASS;
writel_relaxed(regval, MODE_REG(pll));
}
update_vco_tbl(pll);
if (!is_locked(pll)) {
if (pll->slew) {
if (c->rate && dyna_alpha_pll_set_rate(c, c->rate))
WARN(1, "%s: Failed to configure rate\n",
c->dbg_name);
} else {
if (c->rate && alpha_pll_set_rate(c, c->rate))
WARN(1, "%s: Failed to configure rate\n",
c->dbg_name);
}
__init_alpha_pll(c);
return HANDOFF_DISABLED_CLK;
} else if (pll->fsm_en_mask && !is_fsm_mode(MODE_REG(pll))) {
WARN(1, "%s should be in FSM mode but is not\n", c->dbg_name);
}
l_val = readl_relaxed(L_REG(pll));
/* read u64 in two steps to satisfy alignment constraint */
a_val = readl_relaxed(A_REG(pll) + 0x4);
a_val = a_val << 32 | readl_relaxed(A_REG(pll));
/* get upper 32 bits */
a_val = a_val >> (ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH);
alpha_en = readl_relaxed(ALPHA_EN_REG(pll));
alpha_en &= masks->alpha_en_mask;
if (!alpha_en)
a_val = 0;
c->rate = compute_rate(pll, l_val, a_val);
/*
* Unconditionally vote for the PLL; it might be on because of
* another master's vote.
*/
if (pll->fsm_en_mask)
__alpha_pll_vote_enable(pll);
return HANDOFF_ENABLED_CLK;
}
static void fabia_alpha_pll_disable(struct clk *c)
{
struct alpha_pll_clk *pll = to_alpha_pll_clk(c);
unsigned long flags;
spin_lock_irqsave(&alpha_pll_reg_lock, flags);
if (pll->fsm_en_mask)
__alpha_pll_vote_disable(pll);
else
__fabia_alpha_pll_disable(pll);
spin_unlock_irqrestore(&alpha_pll_reg_lock, flags);
}
static void __init_alpha_pll(struct clk *c)
{
struct alpha_pll_clk *pll = to_alpha_pll_clk(c);
struct alpha_pll_masks *masks = pll->masks;
u32 regval;
if (masks->output_mask && pll->enable_config) {
regval = readl_relaxed(OUTPUT_REG(pll));
regval &= ~masks->output_mask;
regval |= pll->enable_config;
writel_relaxed(regval, OUTPUT_REG(pll));
}
if (masks->post_div_mask) {
regval = readl_relaxed(USER_CTL_LO_REG(pll));
regval &= ~masks->post_div_mask;
regval |= pll->post_div_config;
writel_relaxed(regval, USER_CTL_LO_REG(pll));
}
if (pll->slew) {
regval = readl_relaxed(USER_CTL_HI_REG(pll));
regval &= ~PLL_LATCH_INTERFACE;
writel_relaxed(regval, USER_CTL_HI_REG(pll));
}
if (masks->config_ctl_mask) {
regval = readl_relaxed(CFG_CTL_REG(pll));
regval &= ~masks->config_ctl_mask;
regval |= pll->config_ctl_val;
writel_relaxed(regval, CFG_CTL_REG(pll));
}
if (masks->test_ctl_lo_mask) {
regval = readl_relaxed(TEST_CTL_LO_REG(pll));
regval &= ~masks->test_ctl_lo_mask;
regval |= pll->test_ctl_lo_val;
writel_relaxed(regval, TEST_CTL_LO_REG(pll));
}
if (masks->test_ctl_hi_mask) {
regval = readl_relaxed(TEST_CTL_HI_REG(pll));
regval &= ~masks->test_ctl_hi_mask;
regval |= pll->test_ctl_hi_val;
writel_relaxed(regval, TEST_CTL_HI_REG(pll));
}
if (pll->fsm_en_mask)
__set_fsm_mode(MODE_REG(pll));
pll->inited = true;
}
static int alpha_pll_set_rate(struct clk *c, unsigned long rate)
{
struct alpha_pll_clk *pll = to_alpha_pll_clk(c);
struct alpha_pll_masks *masks = pll->masks;
unsigned long flags, freq_hz;
u32 regval, l_val;
int vco_val;
u64 a_val;
freq_hz = round_rate_up(pll, rate, &l_val, &a_val);
if (freq_hz != rate) {
pr_err("alpha_pll: Call clk_set_rate with rounded rates!\n");
return -EINVAL;
}
vco_val = find_vco(pll, freq_hz);
if (IS_ERR_VALUE(vco_val)) {
pr_err("alpha pll: not in a valid vco range\n");
return -EINVAL;
}
/*
* Ensure PLL is off before changing rate. For optimization reasons,
* assume no downstream clock is actively using it. No support
* for dynamic update at the moment.
*/
spin_lock_irqsave(&c->lock, flags);
if (c->count)
alpha_pll_disable(c);
a_val = a_val << (ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH);
writel_relaxed(l_val, L_REG(pll));
__iowrite32_copy(A_REG(pll), &a_val, 2);
if (masks->vco_mask) {
regval = readl_relaxed(VCO_REG(pll));
regval &= ~(masks->vco_mask << masks->vco_shift);
regval |= vco_val << masks->vco_shift;
writel_relaxed(regval, VCO_REG(pll));
}
regval = readl_relaxed(ALPHA_EN_REG(pll));
regval |= masks->alpha_en_mask;
writel_relaxed(regval, ALPHA_EN_REG(pll));
if (c->count)
alpha_pll_enable(c);
spin_unlock_irqrestore(&c->lock, flags);
return 0;
}
static int fabia_alpha_pll_enable(struct clk *c)
{
struct alpha_pll_clk *pll = to_alpha_pll_clk(c);
unsigned long flags;
int rc;
spin_lock_irqsave(&alpha_pll_reg_lock, flags);
if (pll->fsm_en_mask)
rc = __alpha_pll_vote_enable(pll);
else
rc = __fabia_alpha_pll_enable(pll);
spin_unlock_irqrestore(&alpha_pll_reg_lock, flags);
return rc;
}
static int dyna_alpha_pll_set_rate(struct clk *c, unsigned long rate)
{
struct alpha_pll_clk *pll = to_alpha_pll_clk(c);
unsigned long freq_hz, flags;
u32 l_val, vco_val;
u64 a_val;
int ret;
freq_hz = round_rate_up(pll, rate, &l_val, &a_val);
if (freq_hz != rate) {
pr_err("alpha_pll: Call clk_set_rate with rounded rates!\n");
return -EINVAL;
}
vco_val = find_vco(pll, freq_hz);
/*
* Dynamic pll update will not support switching frequencies across
* vco ranges. In those cases fall back to normal alpha set rate.
*/
if (pll->current_vco_val != vco_val) {
ret = alpha_pll_set_rate(c, rate);
if (!ret)
pll->current_vco_val = vco_val;
else
return ret;
return 0;
}
spin_lock_irqsave(&c->lock, flags);
a_val = a_val << (ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH);
writel_relaxed(l_val, L_REG(pll));
__iowrite32_copy(A_REG(pll), &a_val, 2);
/* Ensure that the write above goes through before proceeding. */
mb();
if (c->count)
dyna_alpha_pll_dynamic_update(pll);
spin_unlock_irqrestore(&c->lock, flags);
return 0;
}
static int alpha_pll_enable(struct clk *c)
{
struct alpha_pll_clk *pll = to_alpha_pll_clk(c);
unsigned long flags;
int rc;
if (unlikely(!pll->inited))
__init_alpha_pll(c);
spin_lock_irqsave(&alpha_pll_reg_lock, flags);
if (pll->fsm_en_mask)
rc = __alpha_pll_vote_enable(pll);
else
rc = __alpha_pll_enable(pll, true);
spin_unlock_irqrestore(&alpha_pll_reg_lock, flags);
return rc;
}
static int alpha_pll_enable_hwfsm(struct clk *c)
{
u32 mode;
struct alpha_pll_clk *pll = to_alpha_pll_clk(c);
/* Re-enable HW FSM mode, clear OFFLINE request */
mode = readl_relaxed(MODE_REG(pll));
mode |= PLL_FSM_ENA_BIT;
mode &= ~PLL_OFFLINE_REQ_BIT;
writel_relaxed(mode, MODE_REG(pll));
/* Make sure enable request goes through before waiting for update */
mb();
if (wait_for_update(pll) < 0)
panic("PLL %s failed to lock", c->dbg_name);
return 0;
}
static void __iomem *alpha_pll_list_registers(struct clk *clk, int n,
struct clk_register_data **regs, u32 *size)
{
struct alpha_pll_clk *pll = to_alpha_pll_clk(clk);
static struct clk_register_data data[] = {
{"PLL_MODE", 0x0},
{"PLL_L_VAL", 0x4},
{"PLL_ALPHA_VAL", 0x8},
{"PLL_ALPHA_VAL_U", 0xC},
{"PLL_USER_CTL", 0x10},
{"PLL_CONFIG_CTL", 0x18},
};
if (n)
return ERR_PTR(-EINVAL);
*regs = data;
*size = ARRAY_SIZE(data);
return MODE_REG(pll);
}
static void alpha_pll_disable_hwfsm(struct clk *c)
{
u32 mode;
struct alpha_pll_clk *pll = to_alpha_pll_clk(c);
/* Request PLL_OFFLINE and wait for ack */
mode = readl_relaxed(MODE_REG(pll));
writel_relaxed(mode | PLL_OFFLINE_REQ_BIT, MODE_REG(pll));
while (!(readl_relaxed(MODE_REG(pll)) & PLL_OFFLINE_ACK_BIT))
;
/* Disable HW FSM */
mode = readl_relaxed(MODE_REG(pll));
mode &= ~PLL_FSM_ENA_BIT;
if (pll->offline_bit_workaround)
mode &= ~PLL_OFFLINE_REQ_BIT;
writel_relaxed(mode, MODE_REG(pll));
while (readl_relaxed(MODE_REG(pll)) & PLL_ACTIVE_FLAG)
;
}
static enum handoff fabia_alpha_pll_handoff(struct clk *c)
{
struct alpha_pll_clk *pll = to_alpha_pll_clk(c);
u64 a_val;
u32 l_val, regval;
/* Set the PLL_HW_UPDATE_LOGIC_BYPASS bit before continuing */
regval = readl_relaxed(MODE_REG(pll));
regval |= ALPHA_PLL_HW_UPDATE_LOGIC_BYPASS;
writel_relaxed(regval, MODE_REG(pll));
if (!is_locked(pll)) {
if (c->rate && fabia_alpha_pll_set_rate(c, c->rate))
WARN(1, "%s: Failed to configure rate\n", c->dbg_name);
__init_alpha_pll(c);
return HANDOFF_DISABLED_CLK;
} else if (pll->fsm_en_mask && !is_fsm_mode(MODE_REG(pll))) {
WARN(1, "%s should be in FSM mode but is not\n", c->dbg_name);
}
l_val = readl_relaxed(FABIA_L_REG(pll));
if (pll->fabia_frac_offset)
a_val = readl_relaxed(FABIA_FRAC_OFF(pll));
else
a_val = readl_relaxed(FABIA_FRAC_REG(pll));
c->rate = compute_rate(pll, l_val, a_val);
/*
* Unconditionally vote for the PLL; it might be on because of
* another master's vote.
*/
if (pll->fsm_en_mask)
__alpha_pll_vote_enable(pll);
return HANDOFF_ENABLED_CLK;
}
