static irqreturn_t tps65910_alm_irq(int irq, void *data)
{
struct tps65910_rtc *tps65910_rtc = data;
int ret;
u8 rtc_ctl;
/*Dummy read -- mandatory for status register*/
ret = tps65910_reg_read(tps65910_rtc->tps65910, TPS65910_RTC_STATUS);
if (ret < 0) {
DBG("%s:Failed to read RTC status: %d\n", __func__, ret);
return ret;
}
ret = tps65910_reg_read(tps65910_rtc->tps65910, TPS65910_RTC_STATUS);
if (ret < 0) {
DBG("%s:Failed to read RTC status: %d\n", __func__, ret);
return ret;
}
rtc_ctl = ret&0xff;
//The alarm interrupt keeps its low level, until the micro-controller write 1 in the ALARM bit of the RTC_STATUS_REG register.
ret = tps65910_reg_write(tps65910_rtc->tps65910, TPS65910_RTC_STATUS,rtc_ctl);
if (ret < 0) {
DBG("%s:Failed to read RTC status: %d\n", __func__, ret);
return ret;
}
rtc_update_irq(tps65910_rtc->rtc, 1, RTC_IRQF | RTC_AF);
DBG("%s:irq=%d,rtc_ctl=0x%x\n",__func__,irq,rtc_ctl);
return IRQ_HANDLED;
}
/*
* We will just handle setting the frequency and make use the framework for
* reading the periodic interupts.
*
* @freq: Current periodic IRQ freq:
* bit 0: every second
* bit 1: every minute
* bit 2: every hour
* bit 3: every day
*/
static int tps65910_rtc_irq_set_freq(struct device *dev, int freq)
{
struct tps65910_rtc *tps65910_rtc = dev_get_drvdata(dev);
int ret;
u8 rtc_ctl;
if (freq < 0 || freq > 3)
return -EINVAL;
ret = tps65910_reg_read(tps65910_rtc->tps65910, TPS65910_RTC_INTERRUPTS);
if (ret < 0) {
dev_err(dev, "Failed to read RTC interrupt: %d\n", ret);
return ret;
}
rtc_ctl = ret | freq;
ret = tps65910_reg_write(tps65910_rtc->tps65910, TPS65910_RTC_INTERRUPTS, rtc_ctl);
if (ret < 0) {
dev_err(dev, "Failed to write RTC control: %d\n", ret);
return ret;
}
return ret;
}
static int tps65910_rtc_readtime(struct device *dev, struct rtc_time *tm)
{
struct tps65910_rtc *tps65910_rtc = dev_get_drvdata(dev);
struct tps65910 *tps65910 = tps65910_rtc->tps65910;
int ret;
int count = 0;
unsigned char rtc_data[ALL_TIME_REGS + 1];
u8 rtc_ctl;
/*Dummy read*/
ret = tps65910_reg_read(tps65910, TPS65910_RTC_CTRL);
/* Has the RTC been programmed? */
ret = tps65910_reg_read(tps65910, TPS65910_RTC_CTRL);
if (ret < 0) {
dev_err(dev, "Failed to read RTC control: %d\n", ret);
return ret;
}
rtc_ctl = ret & (~BIT_RTC_CTRL_REG_RTC_V_OPT_M);
ret = tps65910_reg_write(tps65910, TPS65910_RTC_CTRL, rtc_ctl);
if (ret < 0) {
dev_err(dev, "Failed to write RTC control: %d\n", ret);
return ret;
}
/* Read twice to make sure we don't read a corrupt, partially
* incremented, value.
*/
do {
ret = tps65910_bulk_read(tps65910, TPS65910_SECONDS,
ALL_TIME_REGS, rtc_data);
if (ret != 0)
continue;
tm->tm_sec = bcd2bin(rtc_data[0]);
tm->tm_min = bcd2bin(rtc_data[1]);
tm->tm_hour = bcd2bin(rtc_data[2]);
tm->tm_mday = bcd2bin(rtc_data[3]);
tm->tm_mon = bcd2bin(rtc_data[4]) - 1;
tm->tm_year = bcd2bin(rtc_data[5]) + 100;
tm->tm_wday = bcd2bin(rtc_data[6]);
dev_dbg(dev, "RTC date/time %4d-%02d-%02d(%d) %02d:%02d:%02d\n",
1900 + tm->tm_year, tm->tm_mon + 1, tm->tm_mday, tm->tm_wday,
tm->tm_hour, tm->tm_min, tm->tm_sec);
return ret;
} while (++count < RTC_GET_TIME_RETRIES);
dev_err(dev, "Timed out reading current time\n");
return 0;
}
static int tps65910_rtc_probe(struct platform_device *pdev)
{
struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent);
struct tps65910_rtc *tps65910_rtc;
int per_irq;
int alm_irq;
int ret = 0;
u8 rtc_ctl;
struct rtc_time tm;
struct rtc_time tm_def = { // 2012.1.1 12:00:00 Saturday
.tm_wday = 6,
.tm_year = 111,
.tm_mon = 0,
.tm_mday = 1,
.tm_hour = 12,
.tm_min = 0,
.tm_sec = 0,
};
tps65910_rtc = kzalloc(sizeof(*tps65910_rtc), GFP_KERNEL);
if (tps65910_rtc == NULL)
return -ENOMEM;
platform_set_drvdata(pdev, tps65910_rtc);
tps65910_rtc->tps65910 = tps65910;
per_irq = tps65910->irq_base + TPS65910_IRQ_RTC_PERIOD;
alm_irq = tps65910->irq_base + TPS65910_IRQ_RTC_ALARM;
/* Take rtc out of reset */
ret = tps65910_reg_read(tps65910, TPS65910_DEVCTRL);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to read TPS65910_DEVCTRL: %d\n", ret);
return ret;
}
if(ret & BIT_RTC_PWDN)
{
rtc_ctl = ret & (~BIT_RTC_PWDN);
ret = tps65910_reg_write(tps65910, TPS65910_DEVCTRL, rtc_ctl);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to write RTC control: %d\n", ret);
return ret;
}
}
/*start rtc default*/
ret = tps65910_reg_read(tps65910, TPS65910_RTC_CTRL);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to read RTC control: %d\n", ret);
return ret;
}
if(!(ret & BIT_RTC_CTRL_REG_STOP_RTC_M))
{
rtc_ctl = ret | BIT_RTC_CTRL_REG_STOP_RTC_M;
ret = tps65910_reg_write(tps65910, TPS65910_RTC_CTRL, rtc_ctl);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to write RTC control: %d\n", ret);
return ret;
}
}
ret = tps65910_reg_read(tps65910, TPS65910_RTC_STATUS);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to read RTC status: %d\n", ret);
return ret;
}
/*set init time*/
ret = tps65910_rtc_readtime(&pdev->dev, &tm);
if (ret)
{
dev_err(&pdev->dev, "Failed to read RTC time\n");
return ret;
}
ret = rtc_valid_tm(&tm);
if (ret) {
dev_err(&pdev->dev,"invalid date/time and init time\n");
tps65910_rtc_set_time(&pdev->dev, &tm_def); // 2011-01-01 12:00:00
dev_info(&pdev->dev, "set RTC date/time %4d-%02d-%02d(%d) %02d:%02d:%02d\n",
1900 + tm_def.tm_year, tm_def.tm_mon + 1, tm_def.tm_mday, tm_def.tm_wday,
tm_def.tm_hour, tm_def.tm_min, tm_def.tm_sec);
}
device_init_wakeup(&pdev->dev, 1);
tps65910_rtc->rtc = rtc_device_register("tps65910", &pdev->dev,
&tps65910_rtc_ops, THIS_MODULE);
if (IS_ERR(tps65910_rtc->rtc)) {
ret = PTR_ERR(tps65910_rtc->rtc);
goto err;
}
/*request rtc and alarm irq of tps65910*/
ret = request_threaded_irq(per_irq, NULL, tps65910_per_irq,
IRQF_TRIGGER_RISING, "RTC period",
tps65910_rtc);
if (ret != 0) {
dev_err(&pdev->dev, "Failed to request periodic IRQ %d: %d\n",
per_irq, ret);
}
ret = request_threaded_irq(alm_irq, NULL, tps65910_alm_irq,
IRQF_TRIGGER_RISING, "RTC alarm",
tps65910_rtc);
if (ret != 0) {
dev_err(&pdev->dev, "Failed to request alarm IRQ %d: %d\n",
alm_irq, ret);
}
//for rtc irq test
//tps65910_set_bits(tps65910_rtc->tps65910, TPS65910_RTC_INTERRUPTS,
// BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
enable_irq_wake(alm_irq); // so tps65910 alarm irq can wake up system
g_pdev = pdev;
printk("%s:ok\n",__func__);
return 0;
err:
kfree(tps65910_rtc);
return ret;
}
static int __devexit tps65910_rtc_remove(struct platform_device *pdev)
{
struct tps65910_rtc *tps65910_rtc = platform_get_drvdata(pdev);
int per_irq = tps65910_rtc->tps65910->irq_base + TPS65910_IRQ_RTC_PERIOD;
int alm_irq = tps65910_rtc->tps65910->irq_base + TPS65910_IRQ_RTC_ALARM;
free_irq(alm_irq, tps65910_rtc);
free_irq(per_irq, tps65910_rtc);
rtc_device_unregister(tps65910_rtc->rtc);
kfree(tps65910_rtc);
return 0;
}
static const struct dev_pm_ops tps65910_rtc_pm_ops = {
.suspend = tps65910_rtc_suspend,
.resume = tps65910_rtc_resume,
.freeze = tps65910_rtc_freeze,
.thaw = tps65910_rtc_resume,
.restore = tps65910_rtc_resume,
.poweroff = tps65910_rtc_suspend,
};
static struct platform_driver tps65910_rtc_driver = {
.probe = tps65910_rtc_probe,
.remove = __devexit_p(tps65910_rtc_remove),
.driver = {
.name = "tps65910-rtc",
.pm = &tps65910_rtc_pm_ops,
},
};
static ssize_t rtc_tps65910_test_write(struct file *file,
const char __user *buf, size_t count, loff_t *offset)
{
char nr_buf[8];
int nr = 0, ret;
struct platform_device *pdev;
struct rtc_time tm;
struct rtc_wkalrm alrm;
struct tps65910_rtc *tps65910_rtc;
if(count > 3)
return -EFAULT;
ret = copy_from_user(nr_buf, buf, count);
if(ret < 0)
return -EFAULT;
sscanf(nr_buf, "%d", &nr);
if(nr > 5 || nr < 0)
{
printk("%s:data is error\n",__func__);
return -EFAULT;
}
if(!g_pdev)
return -EFAULT;
else
pdev = g_pdev;
tps65910_rtc = dev_get_drvdata(&pdev->dev);
//test rtc time
if(nr == 0)
{
tm.tm_wday = 6;
tm.tm_year = 111;
tm.tm_mon = 0;
tm.tm_mday = 1;
tm.tm_hour = 12;
tm.tm_min = 0;
tm.tm_sec = 0;
ret = tps65910_rtc_set_time(&pdev->dev, &tm); // 2011-01-01 12:00:00
if (ret)
{
dev_err(&pdev->dev, "Failed to set RTC time\n");
return -EFAULT;
}
}
/*set init time*/
ret = tps65910_rtc_readtime(&pdev->dev, &tm);
if (ret)
dev_err(&pdev->dev, "Failed to read RTC time\n");
else
dev_info(&pdev->dev, "RTC date/time %4d-%02d-%02d(%d) %02d:%02d:%02d\n",
1900 + tm.tm_year, tm.tm_mon + 1, tm.tm_mday, tm.tm_wday,
tm.tm_hour, tm.tm_min, tm.tm_sec);
if(!ret)
printk("%s:ok\n",__func__);
else
printk("%s:error\n",__func__);
//test rtc alarm
if(nr == 2)
{
//2000-01-01 00:00:30
if(tm.tm_sec < 30)
{
alrm.time.tm_sec = tm.tm_sec+30;
alrm.time.tm_min = tm.tm_min;
}
else
{
alrm.time.tm_sec = tm.tm_sec-30;
alrm.time.tm_min = tm.tm_min+1;
}
alrm.time.tm_hour = tm.tm_hour;
alrm.time.tm_mday = tm.tm_mday;
alrm.time.tm_mon = tm.tm_mon;
alrm.time.tm_year = tm.tm_year;
tps65910_rtc_alarm_irq_enable(&pdev->dev, 1);
tps65910_rtc_setalarm(&pdev->dev, &alrm);
dev_info(&pdev->dev, "Set alarm %4d-%02d-%02d(%d) %02d:%02d:%02d\n",
1900 + alrm.time.tm_year, alrm.time.tm_mon + 1, alrm.time.tm_mday, alrm.time.tm_wday,
alrm.time.tm_hour, alrm.time.tm_min, alrm.time.tm_sec);
}
if(nr == 3)
{
ret = tps65910_reg_read(tps65910_rtc->tps65910, TPS65910_RTC_STATUS);
if (ret < 0) {
printk("%s:Failed to read RTC status: %d\n", __func__, ret);
return ret;
}
printk("%s:ret=0x%x\n",__func__,ret&0xff);
ret = tps65910_reg_write(tps65910_rtc->tps65910, TPS65910_RTC_STATUS, ret&0xff);
if (ret < 0) {
printk("%s:Failed to read RTC status: %d\n", __func__, ret);
return ret;
}
}
if(nr == 4)
tps65910_rtc_update_irq_enable(&pdev->dev, 1);
if(nr == 5)
tps65910_rtc_update_irq_enable(&pdev->dev, 0);
return count;
}
/*
* Set current time and date in RTC
*/
static int tps65910_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct tps65910_rtc *tps65910_rtc = dev_get_drvdata(dev);
struct tps65910 *tps65910 = tps65910_rtc->tps65910;
int ret;
u8 rtc_ctl;
unsigned char rtc_data[ALL_TIME_REGS + 1];
rtc_data[0] = bin2bcd(tm->tm_sec);
rtc_data[1] = bin2bcd(tm->tm_min);
rtc_data[2] = bin2bcd(tm->tm_hour);
rtc_data[3] = bin2bcd(tm->tm_mday);
rtc_data[4] = bin2bcd(tm->tm_mon + 1);
rtc_data[5] = bin2bcd(tm->tm_year - 100);
rtc_data[6] = bin2bcd(tm->tm_wday);
/*Dummy read*/
ret = tps65910_reg_read(tps65910, TPS65910_RTC_CTRL);
/* Stop RTC while updating the TC registers */
ret = tps65910_reg_read(tps65910, TPS65910_RTC_CTRL);
if (ret < 0) {
dev_err(dev, "Failed to read RTC control: %d\n", ret);
return ret;
}
rtc_ctl = ret & (~BIT_RTC_CTRL_REG_STOP_RTC_M);
ret = tps65910_reg_write(tps65910, TPS65910_RTC_CTRL, rtc_ctl);
if (ret < 0) {
dev_err(dev, "Failed to write RTC control: %d\n", ret);
return ret;
}
/* update all the time registers in one shot */
ret = tps65910_bulk_write(tps65910, TPS65910_SECONDS,
ALL_TIME_REGS, rtc_data);
if (ret < 0) {
dev_err(dev, "Failed to read RTC times: %d\n", ret);
return ret;
}
/*Dummy read*/
ret = tps65910_reg_read(tps65910, TPS65910_RTC_CTRL);
/* Start RTC again */
ret = tps65910_reg_read(tps65910, TPS65910_RTC_CTRL);
if (ret < 0) {
dev_err(dev, "Failed to read RTC control: %d\n", ret);
return ret;
}
rtc_ctl = ret | BIT_RTC_CTRL_REG_STOP_RTC_M;
ret = tps65910_reg_write(tps65910, TPS65910_RTC_CTRL, rtc_ctl);
if (ret < 0) {
dev_err(dev, "Failed to write RTC control: %d\n", ret);
return ret;
}
return 0;
}
int tps65910_pre_init(struct tps65910 *tps65910){
int val = 0;
int i = 0;
int err = -1;
printk("%s,line=%d\n", __func__,__LINE__);
//gpio_request(PMU_POWER_SLEEP, "NULL");
//gpio_direction_output(PMU_POWER_SLEEP, GPIO_HIGH);
val = tps65910_reg_read(tps65910, TPS65910_DEVCTRL2);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_DEVCTRL2 reg\n");
return val;
}
/* Set sleep state active high and allow device turn-off after PWRON long press */
val |= (DEVCTRL2_SLEEPSIG_POL_MASK | DEVCTRL2_PWON_LP_OFF_MASK);
err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL2, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_DEVCTRL2 reg\n");
return err;
}
#if 1
/* set PSKIP=0 */
val = tps65910_reg_read(tps65910, TPS65910_DCDCCTRL);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return val;
}
val &= ~DEVCTRL_DEV_OFF_MASK;
val &= ~DEVCTRL_DEV_SLP_MASK;
err = tps65910_reg_write(tps65910, TPS65910_DCDCCTRL, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_DCDCCTRL reg\n");
return err;
}
#endif
/* Set the maxinum load current */
/* VDD1 */
val = tps65910_reg_read(tps65910, TPS65910_VDD1);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_VDD1 reg\n");
return val;
}
val |= (1<<5); //when 1: 1.5 A
val |= (0x07<<2); //TSTEP[2:0] = 111 : 2.5 mV/¦Ìs(sampling 3 Mhz/5)
err = tps65910_reg_write(tps65910, TPS65910_VDD1, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_VDD1 reg\n");
return err;
}
/* VDD2 */
val = tps65910_reg_read(tps65910, TPS65910_VDD2);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_VDD2 reg\n");
return val;
}
val |= (1<<5); //when 1: 1.5 A
err = tps65910_reg_write(tps65910, TPS65910_VDD2, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_VDD2 reg\n");
return err;
}
/* VIO */
val = tps65910_reg_read(tps65910, TPS65910_VIO);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_VIO reg\n");
return -EIO;
}
val |= (1<<6); //when 01: 1.0 A
err = tps65910_reg_write(tps65910, TPS65910_VIO, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_VIO reg\n");
return err;
}
#if 1
/* Mask ALL interrupts */
err = tps65910_reg_write(tps65910,TPS65910_INT_MSK, 0xFF);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_INT_MSK reg\n");
return err;
}
err = tps65910_reg_write(tps65910, TPS65910_INT_MSK2, 0x03);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_INT_MSK2 reg\n");
return err;
}
/* Set RTC Power, disable Smart Reflex in DEVCTRL_REG */
#if 1
val = 0;
val |= (DEVCTRL_SR_CTL_I2C_SEL_MASK);
err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_DEVCTRL reg\n");
return err;
}
printk(KERN_INFO "TPS65910 Set default voltage.\n");
#endif
#if 0
//read sleep control register for debug
for(i=0; i<6; i++)
{
err = tps65910_reg_read(tps65910, &val, TPS65910_DEVCTRL+i);
if (err) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return -EIO;
}
else
printk("%s.......is 0x%04x\n",__FUNCTION__,val);
}
#endif
#if 1
//sleep control register
/*set func when in sleep mode */
val = tps65910_reg_read(tps65910, TPS65910_DEVCTRL);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return val;
}
val |= (1 << 1);
err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL, val);
if (err) {
printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
\n", TPS65910_VDIG1);
return err;
}
/* open ldo when in sleep mode */
val = tps65910_reg_read(tps65910, TPS65910_SLEEP_KEEP_LDO_ON);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return val;
}
val &= 0;
err = tps65910_reg_write(tps65910, TPS65910_SLEEP_KEEP_LDO_ON, val);
if (err) {
printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
\n", TPS65910_VDIG1);
return err;
}
/*set dc mode when in sleep mode */
val = tps65910_reg_read(tps65910, TPS65910_SLEEP_KEEP_RES_ON);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return val;
}
val |= 0xff;
err = tps65910_reg_write(tps65910, TPS65910_SLEEP_KEEP_RES_ON, val);
if (err) {
printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
\n", TPS65910_VDIG1);
return err;
}
/*close ldo when in sleep mode */
val = tps65910_reg_read(tps65910, TPS65910_SLEEP_SET_LDO_OFF);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return val;
}
val |= 0x0b;
err = tps65910_reg_write(tps65910, TPS65910_SLEEP_SET_LDO_OFF, val);
if (err) {
printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
\n", TPS65910_VDIG1);
return err;
}
#endif
#if 0
//read sleep control register for debug
for(i=0; i<6; i++)
{
err = tps65910_reg_read(tps65910, &val, TPS65910_DEVCTRL+i);
if (err) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return -EIO;
}
else
printk("%s.......is 0x%4x\n",__FUNCTION__,val);
}
#endif
#endif
printk("%s,line=%d\n", __func__,__LINE__);
return 0;
}
int tps65910_pre_init(struct tps65910 *tps65910){
int val = 0;
int i = 0;
int err = -1;
printk("%s,line=%d\n", __func__,__LINE__);
#ifdef CONFIG_RK_CONFIG
if(sram_gpio_init(get_port_config(pmic_slp).gpio, &pmic_sleep) < 0){
printk(KERN_ERR "sram_gpio_init failed\n");
return -EINVAL;
}
if(port_output_init(pmic_slp, 0, "pmic_slp") < 0){
printk(KERN_ERR "port_output_init failed\n");
return -EINVAL;
}
#else
if(sram_gpio_init(PMU_POWER_SLEEP, &pmic_sleep) < 0){
printk(KERN_ERR "sram_gpio_init failed\n");
return -EINVAL;
}
gpio_request(PMU_POWER_SLEEP, "NULL");
gpio_direction_output(PMU_POWER_SLEEP, GPIO_LOW);
#endif
#if 0
/*************set vdd11 (pll) voltage 1.0v********************/
val = tps65910_reg_read(tps65910, TPS65910_VDIG2);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_VDIG2 reg\n");
return val;
}
val &= (~(0x3<<2));
err = tps65910_reg_write(tps65910, TPS65910_VDIG2, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_VDIG2 reg\n");
return err;
}
/****************************************/
#endif
val = tps65910_reg_read(tps65910, TPS65910_DEVCTRL2);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_DEVCTRL2 reg\n");
return val;
}
/* Set sleep state active high and allow device turn-off after PWRON long press */
val |= (DEVCTRL2_SLEEPSIG_POL_MASK | DEVCTRL2_PWON_LP_OFF_MASK);
err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL2, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_DEVCTRL2 reg\n");
return err;
}
#if 1
/* set PSKIP=0 */
val = tps65910_reg_read(tps65910, TPS65910_DCDCCTRL);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return val;
}
val &= ~DEVCTRL_DEV_OFF_MASK;
val &= ~DEVCTRL_DEV_SLP_MASK;
err = tps65910_reg_write(tps65910, TPS65910_DCDCCTRL, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_DCDCCTRL reg\n");
return err;
}
#endif
/* Set the maxinum load current */
/* VDD1 */
val = tps65910_reg_read(tps65910, TPS65910_VDD1);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_VDD1 reg\n");
return val;
}
val |= (1<<5); //when 1: 1.5 A
val &= (~(0x3 <<2));
val |= (0x01<<2); //TSTEP[3:2] = 01 : 12.5 mV/us(sampling 3 Mhz)
err = tps65910_reg_write(tps65910, TPS65910_VDD1, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_VDD1 reg\n");
return err;
}
/* VDD2 */
val = tps65910_reg_read(tps65910, TPS65910_VDD2);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_VDD2 reg\n");
return val;
}
val |= (1<<5); //when 1: 1.5 A
val &= (~(0x3 <<2));
val |= (0x01<<2); //TSTEP[3:2] = 01 : 12.5 mV/us(sampling 3 Mhz)
err = tps65910_reg_write(tps65910, TPS65910_VDD2, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_VDD2 reg\n");
return err;
}
/* VIO */
val = tps65910_reg_read(tps65910, TPS65910_VIO);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_VIO reg\n");
return -EIO;
}
val |= (1<<6); //when 01: 1.0 A
err = tps65910_reg_write(tps65910, TPS65910_VIO, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_VIO reg\n");
return err;
}
#if 1
/* Mask ALL interrupts */
err = tps65910_reg_write(tps65910,TPS65910_INT_MSK, 0xFF);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_INT_MSK reg\n");
return err;
}
err = tps65910_reg_write(tps65910, TPS65910_INT_MSK2, 0x03);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_INT_MSK2 reg\n");
return err;
}
/* Set RTC Power, disable Smart Reflex in DEVCTRL_REG */
#if 1
val = 0;
val |= (DEVCTRL_SR_CTL_I2C_SEL_MASK);
err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_DEVCTRL reg\n");
return err;
}
printk(KERN_INFO "TPS65910 Set default voltage.\n");
#endif
#if 0
//read sleep control register for debug
for(i=0; i<6; i++)
{
err = tps65910_reg_read(tps65910, &val, TPS65910_DEVCTRL+i);
if (err) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return -EIO;
}
else
printk("%s.......is 0x%04x\n",__FUNCTION__,val);
}
#endif
#if 1
//sleep control register
/*set func when in sleep mode */
val = tps65910_reg_read(tps65910, TPS65910_DEVCTRL);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return val;
}
val |= (1 << 1);
err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL, val);
if (err) {
printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
\n", TPS65910_VDIG1);
return err;
}
/* open ldo when in sleep mode */
val = tps65910_reg_read(tps65910, TPS65910_SLEEP_KEEP_LDO_ON);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return val;
}
val &= 0;
err = tps65910_reg_write(tps65910, TPS65910_SLEEP_KEEP_LDO_ON, val);
if (err) {
printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
\n", TPS65910_VDIG1);
return err;
}
/*set dc mode when in sleep mode */
val = tps65910_reg_read(tps65910, TPS65910_SLEEP_KEEP_RES_ON);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return val;
}
val |= 0xff;
val &= ~(0x07); //set vdd1 vdd2 vio in pfm mode when in sleep
err = tps65910_reg_write(tps65910, TPS65910_SLEEP_KEEP_RES_ON, val);
if (err) {
printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
\n", TPS65910_VDIG1);
return err;
}
/*close ldo when in sleep mode */
val = tps65910_reg_read(tps65910, TPS65910_SLEEP_SET_LDO_OFF);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return val;
}
#if defined ( CONFIG_ARCH_RK3026)
val |= 0x2b;
#else
val |= 0x0b;
#endif
err = tps65910_reg_write(tps65910, TPS65910_SLEEP_SET_LDO_OFF, val);
if (err) {
printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
\n", TPS65910_VDIG1);
return err;
}
#endif
#if 0
//read sleep control register for debug
for(i=0; i<6; i++)
{
err = tps65910_reg_read(tps65910, &val, TPS65910_DEVCTRL+i);
if (err) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return -EIO;
}
else
printk("%s.......is 0x%4x\n",__FUNCTION__,val);
}
#endif
#endif
/*****************set arm and logic (dc1&dc2)in pwm ****************/
val = tps65910_reg_read(tps65910, TPS65910_DCDCCTRL);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return val;
}
val &= ~(3<<4);
err = tps65910_reg_write(tps65910, TPS65910_DCDCCTRL, val);
if (err) {
printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
\n", TPS65910_VDIG1);
return err;
}
/************************************************/
printk("%s,line=%d\n", __func__,__LINE__);
return 0;
}
