static int
tzic_attach(device_t dev)
{
struct tzic_softc *sc = device_get_softc(dev);
int i;
uint32_t reg;
if (tzic_sc)
return (ENXIO);
if (bus_alloc_resources(dev, tzic_spec, sc->tzic_res)) {
device_printf(dev, "could not allocate resources\n");
return (ENXIO);
}
arm_post_filter = tzic_post_filter;
/* Distributor Interface */
sc->tzic_bst = rman_get_bustag(sc->tzic_res[0]);
sc->tzic_bsh = rman_get_bushandle(sc->tzic_res[0]);
tzic_sc = sc;
reg = tzic_read_4(TZIC_INTCNTL);
tzic_write_4(TZIC_INTCNTL, INTCNTL_NSEN_MASK|INTCNTL_NSEN|INTCNTL_EN);
reg = tzic_read_4(TZIC_INTCNTL);
tzic_write_4(TZIC_PRIOMASK, 0x1f);
reg = tzic_read_4(TZIC_PRIOMASK);
tzic_write_4(TZIC_SYNCCTRL, 0x02);
reg = tzic_read_4(TZIC_SYNCCTRL);
/* route all interrupts to IRQ. secure interrupts are for FIQ */
for (i = 0; i < 4; i++)
tzic_write_4(TZIC_INTSEC(i), 0xffffffff);
/* disable all interrupts */
for (i = 0; i < 4; i++)
tzic_write_4(TZIC_ENCLEAR(i), 0xffffffff);
return (0);
}
void
arm_mask_irq(uintptr_t nb)
{
tzic_write_4(TZIC_ENCLEAR(nb / 32), (1UL <<(nb % 32)));
}
void
arm_unmask_irq(uintptr_t nb)
{
tzic_write_4(TZIC_ENSET(nb / 32), (1UL <<(nb % 32)));
}
static inline void
tzic_irq_eoi(struct tzic_softc *sc)
{
tzic_write_4(sc, TZIC_PRIOMASK, 0xff);
}
