UINT32 u4VDecReadAVCVLD(UINT32 u4VDecID, UINT32 u4Addr)
{
#if ((CONFIG_CHIP_VER_CURR >= CONFIG_CHIP_VER_MT8560))
u4VDecID = 0;
#endif
UINT32 u4Val;
if (u4VDecID == 0)
{
#ifdef VDEC_SIM_DUMP
u4Val = (u4ReadReg(AVC_VLD_REG_OFFSET0 + u4Addr));
vVDecSimDumpR(u4VDecID, AVC_VLD_REG_OFFSET0, u4Addr, u4Val);
return(u4Val);
#endif
return(u4ReadReg(AVC_VLD_REG_OFFSET0 + u4Addr));
}
else
{
#ifdef VDEC_SIM_DUMP
u4Val = (u4ReadReg(AVC_VLD_REG_OFFSET1 + u4Addr));
vVDecSimDumpR(u4VDecID, AVC_VLD_REG_OFFSET1, u4Addr, u4Val);
return(u4Val);
#endif
return (u4ReadReg(AVC_VLD_REG_OFFSET1 + u4Addr));
}
}
UINT32 u4VDecReadAVCFG(UINT32 u4VDecID, UINT32 u4Addr)
{
#if ((CONFIG_CHIP_VER_CURR >= CONFIG_CHIP_VER_MT8560))
u4VDecID = 0;
#endif
if (u4VDecID == 0)
{
return (u4ReadReg(AVC_FG_REG_OFFSET0 + u4Addr));
}
else
{
return (u4ReadReg(AVC_FG_REG_OFFSET1 + u4Addr));
}
}
UINT32 u4VDecReadAVCMV(UINT32 u4VDecID, UINT32 u4Addr)
{
UINT32 u4Val;
#if ((CONFIG_CHIP_VER_CURR >= CONFIG_CHIP_VER_MT8560))
u4VDecID = 0;
#endif
if (u4VDecID == 0)
{
u4Val = (u4ReadReg(AVC_MV_REG_OFFSET0 + u4Addr));
vVDecSimDumpR(u4VDecID, AVC_MV_REG_OFFSET0, u4Addr, u4Val);
return (u4ReadReg(AVC_MV_REG_OFFSET0 + u4Addr));
}
else
{
u4Val = (u4ReadReg(AVC_MV_REG_OFFSET1 + u4Addr));
vVDecSimDumpR(u4VDecID, AVC_MV_REG_OFFSET1, u4Addr, u4Val);
return u4Val;
}
}
void vVP9RISCRead_MC(UINT32 u4Addr, UINT32* pu4Value , UINT32 u4CoreId)
{
UINT32 VP9_MC_BASE = 0;
if(u4CoreId == 0)
{
VP9_MC_BASE = MC_REG_OFFSET0;
}
else
{
VP9_MC_BASE = MC_REG_OFFSET1;
}
(*pu4Value) = u4ReadReg(VP9_MC_BASE + u4Addr*4);
//(*pu4Value) = DRV_ReadReg( MC_BASE, u4Addr*4 );
SIM_PRINT(" RISCRead_MC(%u, %u); // 0x%08x\n", u4Addr, u4CoreId, (*pu4Value));
}
void vVP9RISCRead_VDEC_TOP(UINT32 u4Addr , UINT32* pu4Value, UINT32 u4CoreId)
{
UINT32 VP9_MISC_BASE = 0;
if(u4CoreId == CORE_0_ID)
{
VP9_MISC_BASE = 0xF6020000;
}
else // currently do not know core 1 settings
{
VP9_MISC_BASE = 0xF6020000;
}
(*pu4Value) = u4ReadReg(VP9_MISC_BASE + u4Addr*4);
//(*pu4Value) = DRV_ReadReg( MISC_BASE, u4Addr*4 );
SIM_PRINT(" RISCRead_VDEC_TOP(%u, %u); // 0x%08x\n", u4Addr, u4CoreId, (*pu4Value));
}
void vVP9RISCRead_PP(UINT32 u4Addr, UINT32* pu4Value, UINT32 u4CoreId )
{
UINT32 VP9_PP_BASE = 0;
if(u4CoreId == CORE_0_ID)
{
VP9_PP_BASE = HEVC_PP_REG_OFFSET0;
}
else
{
//PP_BASE = HEVC_PP_REG_OFFSET1;
}
(*pu4Value) = u4ReadReg(VP9_PP_BASE + u4Addr*4);
//(*pu4Value) = DRV_ReadReg( PP_BASE, u4Addr*4 );
SIM_PRINT(" RISCRead_PP(%u, %u); // 0x%08x", u4Addr, u4CoreId, (*pu4Value));
}
void vVP9RISCRead_BS2(UINT32 u4Addr , UINT32* pu4Value, UINT32 u4CoreId)
{
UINT32 VP9_BS2_BASE = 0;
if(u4CoreId == CORE_0_ID)
{
VP9_BS2_BASE = VDEC_BS2_OFFSET0;
}
else if(u4CoreId == CORE_1_ID)
{
//BS2_BASE = VDEC_BS2_OFFSET1;
}
else
{
//BS2_BASE = LAE_BS2_OFFSET0;
}
(*pu4Value) = u4ReadReg(VP9_BS2_BASE + u4Addr*4);
//(*pu4Value) = DRV_ReadReg( BS2_BASE, u4Addr*4 );
SIM_PRINT(" RISCRead_BS2(%u, %u); // 0x%08x\n", u4Addr, u4CoreId, (*pu4Value));
}
void vVP9RISCRead_VP9_VLD(UINT32 u4Addr , UINT32* pu4Value, UINT32 u4CoreId)
{
UINT32 VP9_VLD_BASE = 0;
if(u4CoreId == CORE_0_ID)
{
VP9_VLD_BASE = VP9_VLD_REG_OFFSET0;
}
else if(u4CoreId == CORE_1_ID)
{
//VLD_BASE = VP9_VLD_REG_OFFSET1;
}
else
{
//VLD_BASE = LAE_VP9_VLD_OFFSET0;
}
(*pu4Value) = u4ReadReg(VP9_VLD_REG_OFFSET0 + u4Addr*4);
//(*pu4Value) = DRV_ReadReg( VLD_BASE, u4Addr*4 );
SIM_PRINT(" RISCRead_VP9_VLD(%u, %u); // 0x%08x\n", u4Addr, u4CoreId, (*pu4Value));
}
void vVP9RISCRead_MV(UINT32 u4Addr, UINT32* pu4Value, UINT32 u4CoreId)
{
UINT32 VP9_MV_BASE = 0;
if(u4CoreId == CORE_0_ID)
{
VP9_MV_BASE = HEVC_MV_REG_OFFSET0;
}
else if(u4CoreId == CORE_1_ID)
{
//MV_BASE = HEVC_MV_REG_OFFSET1;
}
else
{
//MV_BASE = LAE_MV_OFFSET0;
}
(*pu4Value) = u4ReadReg(VP9_MV_BASE + u4Addr*4);
//(*pu4Value) = DRV_ReadReg( MV_BASE, u4Addr*4 );
SIM_PRINT(" RISCRead_MV( %u, %u); /* return 0x%08x */\n", u4Addr, u4CoreId, (*pu4Value));
}
