void uart_putchar(int fd, char ch) {
int uart = (fd == 2) ? s_system_uartno : UART_MAIN;
if (fd == 2 && !debug_enabled) return;
if (ch == '\n') uart_tx_char(uart, '\r');
uart_tx_char(uart, ch);
}
void uart_tx_strn_cooked(pyb_uart_obj_t *self, const char *str, uint len) {
for (const char *top = str + len; str < top; str++) {
if (*str == '\n') {
uart_tx_char(self, '\r');
}
uart_tx_char(self, *str);
}
}
static void uart_system_tx_char(char ch) {
if (ch == '\n') {
uart_tx_char(s_system_uartno, '\r');
uart_tx_char(s_system_uartno, '\n');
} else if (ch != '\r') {
uart_tx_char(s_system_uartno, ch);
}
}
void uart_write(int fd, char *p, size_t len) {
size_t i;
int uart = (fd == 2) ? s_system_uartno : UART_MAIN;
if (fd == 2 && !debug_enabled) return;
for (i = 0; i < len; i++) {
if (p[i] == '\n') uart_tx_char(uart, '\r');
uart_tx_char(uart, p[i]);
}
}
bool uart_tx_strn(pyb_uart_obj_t *self, const char *str, uint len) {
for (const char *top = str + len; str < top; str++) {
if (!uart_tx_char(self, *str)) {
return false;
}
}
return true;
}
int uart_out_str(char *str, int size)
{
int lp;
for (lp = 0; lp < size; lp++)
uart_tx_char(str[lp]);
return lp;
}
/// \method writechar(char)
/// Write a single character on the bus. `char` is an integer to write.
/// Return value: `None`.
STATIC mp_obj_t pyb_uart_writechar(mp_obj_t self_in, mp_obj_t char_in) {
pyb_uart_obj_t *self = self_in;
// get the character to write
uint8_t data = mp_obj_get_int(char_in);
// send the character
if (!uart_tx_char(self, data)) {
nlr_raise(mp_obj_new_exception_arg1(&mp_type_OSError, MP_OBJ_NEW_SMALL_INT(ETIMEDOUT)));
}
return mp_const_none;
}
static size_t IRAM_ATTR uart_write(int fd, const void * data, size_t size)
{
assert(fd >=0 && fd < 3);
const char *data_c = (const char *)data;
uart_dev_t* uart = s_uarts[fd];
/*
* Even though newlib does stream locking on each individual stream, we need
* a dedicated UART lock if two streams (stdout and stderr) point to the
* same UART.
*/
_lock_acquire_recursive(&s_uart_locks[fd]);
for (size_t i = 0; i < size; i++) {
#if CONFIG_NEWLIB_STDOUT_ADDCR
if (data_c[i]=='\n') {
uart_tx_char(uart, '\r');
}
#endif
uart_tx_char(uart, data_c[i]);
}
_lock_release_recursive(&s_uart_locks[fd]);
return size;
}
int main()
{
int val;
adc_init();
uart_init();
timer_init();
while(1)
{
AD0CR |= (1<<24); // Start ADC
while(!(AD0GDR & (1<<31))) ; // Waiting for adc conversion to finish
val = (AD0DR1 & 0xFFC0) >> 6; // Result in bits 15:6
uart_tx_int(val);
uart_tx_char('\r');
delay_ms(100); // To avoid PC from hanging
}
}
void eeprom_read()
{
/***********************WRITING DATA*************************************/
start();
uart_tx_str("\r\nhere\r\n");
devadd1();
location(0x00);
stop();
/******************************************READ********************************************/
start();
devadd2();
for(j=0;j<=5;j++)
{
uart_tx_char(readdata());
}
stop();
}
int __fputc(int c, FILE *stream)
{
uart_tx_char(uart_print_base, c);
return 0;
}
int main()
{
int x,y,z;
adc_init();
uart_init();
lcd_init(); delay(100);
lcd_char('a');
while(1)
{ cmd(0x01); // Clear LCD
AD0CR = 0x01200600; // ADC Stop, select Channel 0
//AD0CR |= 0x01000000; // Start ADC, Channel 0
x = read_adc();
cmd(0x80);
lcd_int(x);
uart_tx_num(x);
uart_tx_char(' ');
AD0CR = 0x01200602;
//AD0CR |= 0x01000000; // Start ADC, Channel 0
y = read_adc();
cmd(0x85);
lcd_int(y);
uart_tx_num(y);
uart_tx_char(' ');
AD0CR = 0x01200604;
//AD0CR |= 0x01000000; // Start ADC, Channel 0
z = read_adc();
cmd(0x8A);
lcd_int(z);
uart_tx_num(z);
uart_tx_str("\r");
if(x>600 )
{
cmd(0x01);
lcd_str("ALERT x = ");
uart_tx_str("\nAlert x");
cmd(0xc0);
lcd_int(x);
delay(1000);
cmd(0x01);
}
if(y<300 )
{
cmd(0x01);
lcd_str("ALERT y = ");
uart_tx_str("\nAlert y");
cmd(0xc0);
lcd_int(y);
delay(1000);
cmd(0x01);
}
delay(100);
}
}
void uart_out_char_check_CR(const char c)
{
uart_tx_char(c);
if (c == '\n')
uart_tx_char('\r');
}