int up_putc(int ch)
{
#ifdef HAVE_SERIAL_CONSOLE
uint8_t imr;
#if defined(CONFIG_USART0_SERIAL_CONSOLE)
usart0_disableusartint(&imr);
#else
usart1_disableusartint(&imr);
#endif
/* Check for LF */
if (ch == '\n')
{
/* Add CR */
up_lowputc('\r');
}
up_lowputc(ch);
#if defined(CONFIG_USART0_SERIAL_CONSOLE)
usart0_restoreusartint(imr);
#else
usart1_restoreusartint(imr);
#endif
#endif
return ch;
}
int up_putc(int ch)
{
#ifdef HAVE_SERIAL_CONSOLE
/* Check for LF */
if (ch == '\n')
{
/* Add CR */
up_lowputc('\r');
}
up_lowputc(ch);
#endif
return ch;
}
void up_lowputs(const char *str)
{
while(*str)
{
up_lowputc(*str++);
}
}
int up_putc(int ch)
{
#if defined(SAMA5_HAVE_UART_CONSOLE) || defined(SAMA5_HAVE_USART_CONSOLE) || \
defined(SAMA5_HAVE_FLEXCOM_CONSOLE) || defined(CONFIG_SAMA5_DBGU_CONSOLE)
/* Check for LF */
if (ch == '\n')
{
/* Add CR */
up_lowputc('\r');
}
up_lowputc(ch);
#endif
return ch;
}
int up_putc(int ch)
{
#ifdef CONSOLE_DEV
/* Disable [E]SCC interrupts and perform the low-level output */
z180_disableuartint(priv);
up_lowputc(ch);
z180_restoreuartint(priv);
return ch;
#endif
}
int up_putc(int ch)
{
#ifdef HAVE_SERIAL_CONSOLE
uint8_t imr;
usart1_disableusartint(&imr);
/* Check for LF */
if (ch == '\n')
{
/* Add CR */
up_lowputc('\r');
}
up_lowputc(ch);
usart1_restoreusartint(imr);
#endif
return ch;
}
static void standby_do_trace(char ch)
{
int i;
/* Stop mode disables HSE/HSI/PLL and wake happens with default system
* clock (MSI, 2Mhz). Reconfigure clocks to enable USART2.
*/
stm32_clockconfig();
/* Stop mode exit traces. */
for (i = 0; i < 4; i++)
up_lowputc(ch);
}
__EXPORT void board_crashdump(uintptr_t currentsp, FAR void *tcb, FAR const uint8_t *filename, int lineno)
{
/* We need a chunk of ram to save the complete context in.
* Since we are going to reboot we will use &_sdata
* which is the lowest memory and the amount we will save
* _should be_ below any resources we need herein.
* Unfortunately this is hard to test. See dead below
*/
fullcontext_s *pdump = (fullcontext_s *)&_sdata;
(void)enter_critical_section();
struct tcb_s *rtcb = (struct tcb_s *)tcb;
/* Zero out everything */
memset(pdump, 0, sizeof(fullcontext_s));
/* Save Info */
pdump->info.lineno = lineno;
if (filename) {
int offset = 0;
unsigned int len = strlen((char *)filename) + 1;
if (len > sizeof(pdump->info.filename)) {
offset = len - sizeof(pdump->info.filename) ;
}
strncpy(pdump->info.filename, (char *)&filename[offset], sizeof(pdump->info.filename));
}
/* Save the value of the pointer for current_regs as debugging info.
* It should be NULL in case of an ASSERT and will aid in cross
* checking the validity of system memory at the time of the
* fault.
*/
pdump->info.current_regs = (uintptr_t) CURRENT_REGS;
/* Save Context */
#if CONFIG_TASK_NAME_SIZE > 0
strncpy(pdump->info.name, rtcb->name, CONFIG_TASK_NAME_SIZE);
#endif
pdump->info.pid = rtcb->pid;
/* If current_regs is not NULL then we are in an interrupt context
* and the user context is in current_regs else we are running in
* the users context
*/
if (CURRENT_REGS) {
pdump->info.stacks.interrupt.sp = currentsp;
pdump->info.flags |= (eRegsPresent | eUserStackPresent | eIntStackPresent);
memcpy(pdump->info.regs, (void *)CURRENT_REGS, sizeof(pdump->info.regs));
pdump->info.stacks.user.sp = pdump->info.regs[REG_R13];
} else {
/* users context */
pdump->info.flags |= eUserStackPresent;
pdump->info.stacks.user.sp = currentsp;
}
if (pdump->info.pid == 0) {
pdump->info.stacks.user.top = g_idle_topstack - 4;
pdump->info.stacks.user.size = CONFIG_IDLETHREAD_STACKSIZE;
} else {
pdump->info.stacks.user.top = (uint32_t) rtcb->adj_stack_ptr;
pdump->info.stacks.user.size = (uint32_t) rtcb->adj_stack_size;;
}
#if CONFIG_ARCH_INTERRUPTSTACK > 3
/* Get the limits on the interrupt stack memory */
pdump->info.stacks.interrupt.top = (uint32_t)&g_intstackbase;
pdump->info.stacks.interrupt.size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
/* If In interrupt Context save the interrupt stack data centered
* about the interrupt stack pointer
*/
if ((pdump->info.flags & eIntStackPresent) != 0) {
stack_word_t *ps = (stack_word_t *) pdump->info.stacks.interrupt.sp;
copy_reverse(pdump->istack, &ps[arraySize(pdump->istack) / 2], arraySize(pdump->istack));
}
/* Is it Invalid? */
if (!(pdump->info.stacks.interrupt.sp <= pdump->info.stacks.interrupt.top &&
pdump->info.stacks.interrupt.sp > pdump->info.stacks.interrupt.top - pdump->info.stacks.interrupt.size)) {
pdump->info.flags |= eInvalidIntStackPrt;
}
#endif
/* If In interrupt context or User save the user stack data centered
* about the user stack pointer
*/
if ((pdump->info.flags & eUserStackPresent) != 0) {
stack_word_t *ps = (stack_word_t *) pdump->info.stacks.user.sp;
copy_reverse(pdump->ustack, &ps[arraySize(pdump->ustack) / 2], arraySize(pdump->ustack));
}
/* Is it Invalid? */
if (!(pdump->info.stacks.user.sp <= pdump->info.stacks.user.top &&
pdump->info.stacks.user.sp > pdump->info.stacks.user.top - pdump->info.stacks.user.size)) {
pdump->info.flags |= eInvalidUserStackPtr;
}
int rv = stm32_bbsram_savepanic(HARDFAULT_FILENO, (uint8_t *)pdump, sizeof(fullcontext_s));
/* Test if memory got wiped because of using _sdata */
if (rv == -ENXIO) {
char *dead = "Memory wiped - dump not saved!";
while (*dead) {
up_lowputc(*dead++);
}
} else if (rv == -ENOSPC) {
/* hard fault again */
up_lowputc('!');
}
#if defined(CONFIG_BOARD_RESET_ON_CRASH)
px4_systemreset(false);
#endif
}
void up_boot_standby_mode(void)
{
uint32_t gpio_off_mask;
uint32_t regval;
int i;
DEBUGASSERT((getreg32(STM32_PWR_CR) & PWR_CR_DBP) != 0);
/*
* This function is called from up_boot.c, stm32_boardinitialize(). OS is not
* running yet. Regulators and chip-selects have been initialized. IWDG not
* enabled. If board has HWWDG, we must enable it from this function before
* going to standby mode.
*/
regval = getreg32(CONFIG_STANDBYMODE_MAGIC_BKREG);
if (regval != CONFIG_STANDBYMODE_MAGIC)
{
g_board_wakeup_from_standby = (regval == CONFIG_STANDBYMODE_MAGIC + 1);
/* Standby mode was not requested, continue with regular boot. */
putreg32(0, CONFIG_STANDBYMODE_MAGIC_BKREG);
for (i = 0; i < 4; i++)
up_lowputc('r');
return;
}
#if defined(CONFIG_STM32_DFU) || defined (CONFIG_BOARD_HALTIAN_HWWDG)
up_irqinitialize();
#endif
/* Go into standby mode. */
putreg32(CONFIG_STANDBYMODE_MAGIC + 1, CONFIG_STANDBYMODE_MAGIC_BKREG);
for (i = 0; i < 4; i++)
up_lowputc('s');
/* Setup bootloader to jump directly to firmware. */
putreg32(BOARD_FIRMWARE_BASE_ADDR, CONFIG_BOOTLOADER_ADDR_BKREG);
/* Now disable backup register access. If following interrupt handlers
* access backup registers, they need to make sure to re-enable access. */
stm32_pwr_enablebkp(false);
while (true)
{
/* Configure SDcard pins. */
gpio_initialize_sdcard_pins();
/* Configure display GPIOs. */
gpio_off_mask = ~(GPIO_PUPD_MASK | GPIO_MODE_MASK | GPIO_OUTPUT_SET);
stm32_configgpio(GPIO_CHIP_SELECT_DISPLAY);
stm32_configgpio(GPIO_LCD_SSD1309_CMDDATA);
stm32_configgpio(GPIO_LCD_SSD1309_RESET);
stm32_configgpio((GPIO_SPI2_MOSI & gpio_off_mask) | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT);
stm32_configgpio((GPIO_SPI2_SCK & gpio_off_mask) | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT);
/* Reconfigure GPIO's for stop mode (most pins are setup as analog input). */
up_reconfigure_gpios_for_pmstop();
/* We must kick HWWDG even from standby mode, else it resets device. */
board_wdginitialize_autokick(hwwdg_irq_in_standby);
/* Setup 'power'-button as EXTI for wake-up. */
stm32_configgpio(GPIO_BTN_POWERKEY);
stm32_gpiosetevent(GPIO_BTN_POWERKEY, true, false, true,
button_pressed_down_handler);
/* Our standby-mode is really ARM core's stop-mode.
Enter stop-mode with MCU internal regulator in low-power mode. */
(void)stm32_pmstop(true);
standby_do_trace('p');
}
}
void stm32_boardinitialize(void)
{
#ifdef BOARD_HAS_BOOTLOADER
/* Check if IWDG is enabled by bootloader. This is the case when
* CONFIG_BOOTLOADER_NOWD_BKREG has lowest bit cleared.
*/
if ((getreg32(CONFIG_BOOTLOADER_NOWD_BKREG) & 1) == 0)
{
int i;
/* Bootloader has enabled IWDG. This happens after POR-reset (since
* backup-registers have been reset to zero) and after firmware update.
*
* Disabling IWDG is used as early boot firmware check (new firmware
* started). We now enable NOWD flag and do reset loop with ADDR value
* set to application firmware.
*
* If firmware does not manage to do early boot and gets stuck, IWDG will
* reset device and bootloader will either attempt to flash backup
* firmware or will reset loop by IWDG until 'current boot try count'
* reaches threshold and bootloader boots device to DFU-mode.
*/
for (i = 0; i < 4; i++)
up_lowputc('>');
/* Enable BKREG writing. */
stm32_pwr_enablebkp(true);
/* Make bootloader disable IWDG. */
putreg32(1, CONFIG_BOOTLOADER_NOWD_BKREG);
/* Setup bootloader to jump directly to firmware. */
putreg32(BOARD_FIRMWARE_BASE_ADDR, CONFIG_BOOTLOADER_ADDR_BKREG);
/* Disable BKREG writing. */
stm32_pwr_enablebkp(false);
/* Do system reset. */
board_systemreset();
}
#endif /* BOARD_HAS_BOOTLOADER */
#if defined(CONFIG_ASSERT_COUNT_BKREG)
/* Check value of assert counter (note: does not enable/disable BKREG access
* with argument==0). */
if (up_add_assert_count(0) >= CONFIG_ASSERT_COUNT_TO_DFU_MODE)
{
const char *str = "\nToo many ASSERT resets; something wrong with software. Forcing DFU mode!\n";
while (*str)
up_lowputc(*str++);
up_mdelay(500);
up_reset_to_system_bootloader();
}
#endif
/* Setup GPIOs based on HW version. */
up_configure_dynamic_gpios();
/* Configure MCU so that debugging is possible in idle modes. */
#ifdef CONFIG_STM32_KEEP_CORE_CLOCK_ENABLED_IN_IDLE_MODES
uint32_t cr = getreg32(STM32_DBGMCU_CR);
cr |= DBGMCU_CR_STANDBY | DBGMCU_CR_STOP | DBGMCU_CR_SLEEP;
putreg32(cr, STM32_DBGMCU_CR);
#endif
#ifdef CONFIG_BOARD_MCO_SYSCLK
/* Output SYSCLK to MCO pin for clock measurements. */
stm32_configgpio(GPIO_MCO);
stm32_mcodivconfig(RCC_CFGR_MCOSEL_SYSCLK, RCC_CFGR_MCOPRE_DIV4);
#endif
/* Configure on-board LEDs if LED support has been selected. */
#ifdef CONFIG_ARCH_LEDS
board_led_initialize();
#endif
/* Configure chip-select pins. */
board_initialize_chipselects();
/* Configure SDcard pins (needs to be after chip-select init, to pull SDcard
* CS down). */
gpio_initialize_sdcard_pins();
/* Configure power control pins. */
board_initialize_pwrctl_pins();
/* Initialize modem gpios. */
up_modem_initialize_gpios();
/* Initialize unused gpio pads. */
gpio_initialize_unused_pads();
/* Enable BKREG writing. */
stm32_pwr_enablebkp(true);
/* Reset 'current boot try count' for bootloader. */
putreg32(0, CONFIG_BOOTLOADER_CBTC_BKREG);
/* Make bootloader disable IWDG. */
putreg32(1, CONFIG_BOOTLOADER_NOWD_BKREG);
/* Check if we need to enter standby/power-off mode. */
up_boot_standby_mode();
/* Disable BKREG writing. */
stm32_pwr_enablebkp(false);
/* Force enable capsense and 9-axis for duration
* of I2C initialization. After bus initialization
* is done, this is undone and drivers will take care
* of requesting power for themselves.
*/
board_pwrctl_get(PWRCTL_SWITCH_CAPSENSE_SENSOR);
board_pwrctl_get(PWRCTL_SWITCH_9AXIS_INERTIAL_SENSOR);
/* Flash mass-erase can leave option-bytes is bad shape, restore defaults if
* needed. */
up_check_and_restore_valid_optionbytes();
/* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function
* stm32_spiinitialize() has been brought into the link.
*/
#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3)
if (stm32_spiinitialize)
{
stm32_spiinitialize();
}
#endif
/* Give early information about reset reason. */
print_reset_reason();
}
static void print_reset_reason(void)
{
uint32_t breason;
breason = board_reset_get_reason(false);
up_lowputc('_');
if (breason & BOARD_RESET_REASON_LOW_POWER)
up_lowputc('L');
if (breason & BOARD_RESET_REASON_WINDOW_WATCHDOG)
up_lowputc('W');
if (breason & BOARD_RESET_REASON_INDEPENDENT_WATCHDOG)
up_lowputc('I');
if (breason & BOARD_RESET_REASON_SOFTWARE)
up_lowputc('S');
if (breason & BOARD_RESET_REASON_POR_PDR)
up_lowputc('P');
if (breason & BOARD_RESET_REASON_NRST_PIN)
up_lowputc('R');
if (breason & BOARD_RESET_REASON_OPTIONS_BYTES_LOADING)
up_lowputc('O');
if (breason & BOARD_RESET_REASON_HARDFAULT)
up_lowputc('H');
if (breason & BOARD_RESET_REASON_STANDBY_WAKEUP)
up_lowputc('^');
up_lowputc('_');
}
static void up_check_and_restore_valid_optionbytes(void)
{
static const uint32_t reset_optb[][2] = {
/* Default option bytes for STM32L162VE. */
{ 0x1FF80004, 0xFF0700F8 },
{ 0x1FF80008, 0xFFFF0000 },
{ 0x1FF8000C, 0xFFFF0000 },
{ 0x1FF80010, 0xFFFF0000 },
{ 0x1FF80014, 0xFFFF0000 },
{ 0x1FF80018, 0xFFFF0000 },
{ 0x1FF8001C, 0xFFFF0000 },
{ 0x1FF80080, 0xFFFF0000 },
{ 0x1FF80084, 0xFFFF0000 },
{ 0x1FF80000, 0xFF5500AA },
{ 0x0, 0x0 },
};
int i;
char buf[64];
const char *str;
int modcount = 0;
if (!(getreg32(STM32_FLASH_SR) & (FLASH_SR_OPTVERR | FLASH_SR_OPTVERRUSR)))
return;
snprintf(buf, sizeof(buf), "\nSTM32_FLASH_SR: %08X\n", getreg32(STM32_FLASH_SR));
str = buf;
while (*str)
up_lowputc(*str++);
for (i = 0; reset_optb[i][0] != 0x0; i++)
{
snprintf(buf, sizeof(buf), "%08X: %08X\n",
reset_optb[i][0],
*(const uint32_t *)reset_optb[i][0]);
str = buf;
while (*str)
up_lowputc(*str++);
}
stm32_ob_unlock();
/* Clear pending status flags. */
putreg32(FLASH_SR_WRPERR | FLASH_SR_PGAERR |
FLASH_SR_SIZERR | FLASH_SR_OPTVERR |
FLASH_SR_OPTVERRUSR | FLASH_SR_RDERR, STM32_FLASH_SR);
for (i = 0; reset_optb[i][0] != 0x0; i++)
{
if (*(const uint32_t *)reset_optb[i][0] == reset_optb[i][1])
continue;
snprintf(buf, sizeof(buf), "Programming %08X: %08X => %08X\n",
reset_optb[i][0],
*(const uint32_t *)reset_optb[i][0],
reset_optb[i][1]);
str = buf;
while (*str)
up_lowputc(*str++);
putreg32(reset_optb[i][1], reset_optb[i][0]);
/* ... and wait to complete. */
while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY);
/* Verify */
if (getreg32(STM32_FLASH_SR) & (FLASH_SR_WRPERR | FLASH_SR_PGAERR |
FLASH_SR_SIZERR | FLASH_SR_RDERR))
{
snprintf(buf, sizeof(buf), "Failed to program %08X!\n",
reset_optb[i][0]);
str = buf;
while (*str)
up_lowputc(*str++);
goto err;
}
if (getreg32(reset_optb[i][0]) != reset_optb[i][1])
{
snprintf(buf, sizeof(buf), "Failed to verify %08X, reads %08X.\n",
reset_optb[i][0], getreg32(reset_optb[i][0]));
str = buf;
while (*str)
up_lowputc(*str++);
goto err;
}
modcount++;
}
putreg32(FLASH_SR_OPTVERR | FLASH_SR_OPTVERRUSR, STM32_FLASH_SR);
stm32_ob_lock();
if (modcount == 0)
return;
err:
while (1)
up_systemreset();
}
void os_start(void)
{
up_lowputc('X');
up_lowputc('\n');
for (;;);
}
uint32_t *up_doirq(int irq, uint32_t *regs)
{
up_lowputc('I');
up_lowputc('\n');
for (;;);
}
int irq_attach(int irq, xcpt_t isr)
{
up_lowputc('A');
up_lowputc('\n');
for (;;);
}
void up_assert(const uint8_t *filename, int lineno)
{
up_lowputc('?');
up_lowputc('\n');
for (;;);
}