void *
st_pbo_create_vs(struct st_context *st)
{
struct pipe_screen *pscreen = st->pipe->screen;
bool use_nir = PIPE_SHADER_IR_NIR ==
pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX,
PIPE_SHADER_CAP_PREFERRED_IR);
if (use_nir) {
unsigned inputs[] = { VERT_ATTRIB_POS, SYSTEM_VALUE_INSTANCE_ID, };
unsigned outputs[] = { VARYING_SLOT_POS, VARYING_SLOT_LAYER };
return st_nir_make_passthrough_shader(st, "st/pbo VS",
MESA_SHADER_VERTEX,
st->pbo.layers ? 2 : 1,
inputs, outputs, NULL, (1 << 1));
}
struct ureg_program *ureg;
struct ureg_src in_pos;
struct ureg_src in_instanceid;
struct ureg_dst out_pos;
struct ureg_dst out_layer;
ureg = ureg_create(PIPE_SHADER_VERTEX);
if (!ureg)
return NULL;
in_pos = ureg_DECL_vs_input(ureg, TGSI_SEMANTIC_POSITION);
out_pos = ureg_DECL_output(ureg, TGSI_SEMANTIC_POSITION, 0);
if (st->pbo.layers) {
in_instanceid = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_INSTANCEID, 0);
if (!st->pbo.use_gs)
out_layer = ureg_DECL_output(ureg, TGSI_SEMANTIC_LAYER, 0);
}
/* out_pos = in_pos */
ureg_MOV(ureg, out_pos, in_pos);
if (st->pbo.layers) {
if (st->pbo.use_gs) {
/* out_pos.z = i2f(gl_InstanceID) */
ureg_I2F(ureg, ureg_writemask(out_pos, TGSI_WRITEMASK_Z),
ureg_scalar(in_instanceid, TGSI_SWIZZLE_X));
} else {
/* out_layer = gl_InstanceID */
ureg_MOV(ureg, ureg_writemask(out_layer, TGSI_WRITEMASK_X),
ureg_scalar(in_instanceid, TGSI_SWIZZLE_X));
}
}
ureg_END(ureg);
return ureg_create_shader_and_destroy(ureg, st->pipe);
}
/**
* This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
* VS passes its outputs to TES directly, so the fixed-function shader only
* has to write TESSOUTER and TESSINNER.
*/
void *si_create_fixed_func_tcs(struct si_context *sctx)
{
struct ureg_src outer, inner;
struct ureg_dst tessouter, tessinner;
struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
if (!ureg)
return NULL;
outer = ureg_DECL_system_value(ureg,
TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0);
inner = ureg_DECL_system_value(ureg,
TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0);
tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
ureg_MOV(ureg, tessouter, outer);
ureg_MOV(ureg, tessinner, inner);
ureg_END(ureg);
return ureg_create_shader_and_destroy(ureg, &sctx->b);
}
void *
st_pbo_create_vs(struct st_context *st)
{
struct ureg_program *ureg;
struct ureg_src in_pos;
struct ureg_src in_instanceid;
struct ureg_dst out_pos;
struct ureg_dst out_layer;
ureg = ureg_create(PIPE_SHADER_VERTEX);
if (!ureg)
return NULL;
in_pos = ureg_DECL_vs_input(ureg, TGSI_SEMANTIC_POSITION);
out_pos = ureg_DECL_output(ureg, TGSI_SEMANTIC_POSITION, 0);
if (st->pbo.layers) {
in_instanceid = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_INSTANCEID, 0);
if (!st->pbo.use_gs)
out_layer = ureg_DECL_output(ureg, TGSI_SEMANTIC_LAYER, 0);
}
/* out_pos = in_pos */
ureg_MOV(ureg, out_pos, in_pos);
if (st->pbo.layers) {
if (st->pbo.use_gs) {
/* out_pos.z = i2f(gl_InstanceID) */
ureg_I2F(ureg, ureg_writemask(out_pos, TGSI_WRITEMASK_Z),
ureg_scalar(in_instanceid, TGSI_SWIZZLE_X));
} else {
/* out_layer = gl_InstanceID */
ureg_MOV(ureg, out_layer, in_instanceid);
}
}
ureg_END(ureg);
return ureg_create_shader_and_destroy(ureg, st->pipe);
}
/**
* Translate Mesa program to TGSI format.
* \param program the program to translate
* \param numInputs number of input registers used
* \param inputMapping maps Mesa fragment program inputs to TGSI generic
* input indexes
* \param inputSemanticName the TGSI_SEMANTIC flag for each input
* \param inputSemanticIndex the semantic index (ex: which texcoord) for
* each input
* \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
* \param numOutputs number of output registers used
* \param outputMapping maps Mesa fragment program outputs to TGSI
* generic outputs
* \param outputSemanticName the TGSI_SEMANTIC flag for each output
* \param outputSemanticIndex the semantic index (ex: which texcoord) for
* each output
*
* \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
*/
enum pipe_error
st_translate_mesa_program(
struct gl_context *ctx,
uint procType,
struct ureg_program *ureg,
const struct gl_program *program,
GLuint numInputs,
const GLuint inputMapping[],
const ubyte inputSemanticName[],
const ubyte inputSemanticIndex[],
const GLuint interpMode[],
GLuint numOutputs,
const GLuint outputMapping[],
const ubyte outputSemanticName[],
const ubyte outputSemanticIndex[],
boolean passthrough_edgeflags,
boolean clamp_color)
{
struct st_translate translate, *t;
unsigned i;
enum pipe_error ret = PIPE_OK;
assert(numInputs <= ARRAY_SIZE(t->inputs));
assert(numOutputs <= ARRAY_SIZE(t->outputs));
t = &translate;
memset(t, 0, sizeof *t);
t->procType = procType;
t->inputMapping = inputMapping;
t->outputMapping = outputMapping;
t->ureg = ureg;
/*_mesa_print_program(program);*/
/*
* Declare input attributes.
*/
if (procType == TGSI_PROCESSOR_FRAGMENT) {
for (i = 0; i < numInputs; i++) {
t->inputs[i] = ureg_DECL_fs_input(ureg,
inputSemanticName[i],
inputSemanticIndex[i],
interpMode[i]);
}
if (program->InputsRead & VARYING_BIT_POS) {
/* Must do this after setting up t->inputs, and before
* emitting constant references, below:
*/
emit_wpos(st_context(ctx), t, program, ureg);
}
if (program->InputsRead & VARYING_BIT_FACE) {
emit_face_var( t, program );
}
/*
* Declare output attributes.
*/
for (i = 0; i < numOutputs; i++) {
switch (outputSemanticName[i]) {
case TGSI_SEMANTIC_POSITION:
t->outputs[i] = ureg_DECL_output( ureg,
TGSI_SEMANTIC_POSITION, /* Z / Depth */
outputSemanticIndex[i] );
t->outputs[i] = ureg_writemask( t->outputs[i],
TGSI_WRITEMASK_Z );
break;
case TGSI_SEMANTIC_STENCIL:
t->outputs[i] = ureg_DECL_output( ureg,
TGSI_SEMANTIC_STENCIL, /* Stencil */
outputSemanticIndex[i] );
t->outputs[i] = ureg_writemask( t->outputs[i],
TGSI_WRITEMASK_Y );
break;
case TGSI_SEMANTIC_COLOR:
t->outputs[i] = ureg_DECL_output( ureg,
TGSI_SEMANTIC_COLOR,
outputSemanticIndex[i] );
break;
default:
debug_assert(0);
return 0;
}
}
}
else if (procType == TGSI_PROCESSOR_GEOMETRY) {
for (i = 0; i < numInputs; i++) {
t->inputs[i] = ureg_DECL_input(ureg,
inputSemanticName[i],
inputSemanticIndex[i], 0, 1);
}
for (i = 0; i < numOutputs; i++) {
t->outputs[i] = ureg_DECL_output( ureg,
outputSemanticName[i],
outputSemanticIndex[i] );
}
}
else {
assert(procType == TGSI_PROCESSOR_VERTEX);
for (i = 0; i < numInputs; i++) {
t->inputs[i] = ureg_DECL_vs_input(ureg, i);
}
for (i = 0; i < numOutputs; i++) {
t->outputs[i] = ureg_DECL_output( ureg,
outputSemanticName[i],
outputSemanticIndex[i] );
if (outputSemanticName[i] == TGSI_SEMANTIC_FOG) {
/* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
ureg_MOV(ureg,
ureg_writemask(t->outputs[i], TGSI_WRITEMASK_YZW),
ureg_imm4f(ureg, 0.0f, 0.0f, 0.0f, 1.0f));
t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_X);
}
}
if (passthrough_edgeflags)
emit_edgeflags( t, program );
}
/* Declare address register.
*/
if (program->NumAddressRegs > 0) {
debug_assert( program->NumAddressRegs == 1 );
t->address[0] = ureg_DECL_address( ureg );
}
/* Declare misc input registers
*/
{
GLbitfield sysInputs = program->SystemValuesRead;
unsigned numSys = 0;
for (i = 0; sysInputs; i++) {
if (sysInputs & (1 << i)) {
unsigned semName = _mesa_sysval_to_semantic[i];
t->systemValues[i] = ureg_DECL_system_value(ureg, numSys, semName, 0);
if (semName == TGSI_SEMANTIC_INSTANCEID ||
semName == TGSI_SEMANTIC_VERTEXID) {
/* From Gallium perspective, these system values are always
* integer, and require native integer support. However, if
* native integer is supported on the vertex stage but not the
* pixel stage (e.g, i915g + draw), Mesa will generate IR that
* assumes these system values are floats. To resolve the
* inconsistency, we insert a U2F.
*/
struct st_context *st = st_context(ctx);
struct pipe_screen *pscreen = st->pipe->screen;
assert(procType == TGSI_PROCESSOR_VERTEX);
assert(pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS));
(void) pscreen; /* silence non-debug build warnings */
if (!ctx->Const.NativeIntegers) {
struct ureg_dst temp = ureg_DECL_local_temporary(t->ureg);
ureg_U2F( t->ureg, ureg_writemask(temp, TGSI_WRITEMASK_X), t->systemValues[i]);
t->systemValues[i] = ureg_scalar(ureg_src(temp), 0);
}
}
numSys++;
sysInputs &= ~(1 << i);
}
}
}
if (program->IndirectRegisterFiles & (1 << PROGRAM_TEMPORARY)) {
/* If temps are accessed with indirect addressing, declare temporaries
* in sequential order. Else, we declare them on demand elsewhere.
*/
for (i = 0; i < program->NumTemporaries; i++) {
/* XXX use TGSI_FILE_TEMPORARY_ARRAY when it's supported by ureg */
t->temps[i] = ureg_DECL_temporary( t->ureg );
}
}
/* Emit constants and immediates. Mesa uses a single index space
* for these, so we put all the translated regs in t->constants.
*/
if (program->Parameters) {
t->constants = calloc( program->Parameters->NumParameters,
sizeof t->constants[0] );
if (t->constants == NULL) {
ret = PIPE_ERROR_OUT_OF_MEMORY;
goto out;
}
for (i = 0; i < program->Parameters->NumParameters; i++) {
switch (program->Parameters->Parameters[i].Type) {
case PROGRAM_STATE_VAR:
case PROGRAM_UNIFORM:
t->constants[i] = ureg_DECL_constant( ureg, i );
break;
/* Emit immediates only when there's no indirect addressing of
* the const buffer.
* FIXME: Be smarter and recognize param arrays:
* indirect addressing is only valid within the referenced
* array.
*/
case PROGRAM_CONSTANT:
if (program->IndirectRegisterFiles & PROGRAM_ANY_CONST)
t->constants[i] = ureg_DECL_constant( ureg, i );
else
t->constants[i] =
ureg_DECL_immediate( ureg,
(const float*) program->Parameters->ParameterValues[i],
4 );
break;
default:
break;
}
}
}
/* texture samplers */
for (i = 0; i < ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxTextureImageUnits; i++) {
if (program->SamplersUsed & (1 << i)) {
t->samplers[i] = ureg_DECL_sampler( ureg, i );
}
}
/* Emit each instruction in turn:
*/
for (i = 0; i < program->NumInstructions; i++) {
set_insn_start( t, ureg_get_instruction_number( ureg ));
compile_instruction( ctx, t, &program->Instructions[i], clamp_color );
}
/* Fix up all emitted labels:
*/
for (i = 0; i < t->labels_count; i++) {
ureg_fixup_label( ureg,
t->labels[i].token,
t->insn[t->labels[i].branch_target] );
}
out:
free(t->insn);
free(t->labels);
free(t->constants);
if (t->error) {
debug_printf("%s: translate error flag set\n", __func__);
}
return ret;
}
void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
unsigned num_layers)
{
unsigned vs_blit_property;
void **vs;
switch (type) {
case UTIL_BLITTER_ATTRIB_NONE:
vs = num_layers > 1 ? &sctx->vs_blit_pos_layered :
&sctx->vs_blit_pos;
vs_blit_property = SI_VS_BLIT_SGPRS_POS;
break;
case UTIL_BLITTER_ATTRIB_COLOR:
vs = num_layers > 1 ? &sctx->vs_blit_color_layered :
&sctx->vs_blit_color;
vs_blit_property = SI_VS_BLIT_SGPRS_POS_COLOR;
break;
case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
assert(num_layers == 1);
vs = &sctx->vs_blit_texcoord;
vs_blit_property = SI_VS_BLIT_SGPRS_POS_TEXCOORD;
break;
default:
assert(0);
return NULL;
}
if (*vs)
return *vs;
struct ureg_program *ureg = ureg_create(PIPE_SHADER_VERTEX);
if (!ureg)
return NULL;
/* Tell the shader to load VS inputs from SGPRs: */
ureg_property(ureg, TGSI_PROPERTY_VS_BLIT_SGPRS, vs_blit_property);
ureg_property(ureg, TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION, true);
/* This is just a pass-through shader with 1-3 MOV instructions. */
ureg_MOV(ureg,
ureg_DECL_output(ureg, TGSI_SEMANTIC_POSITION, 0),
ureg_DECL_vs_input(ureg, 0));
if (type != UTIL_BLITTER_ATTRIB_NONE) {
ureg_MOV(ureg,
ureg_DECL_output(ureg, TGSI_SEMANTIC_GENERIC, 0),
ureg_DECL_vs_input(ureg, 1));
}
if (num_layers > 1) {
struct ureg_src instance_id =
ureg_DECL_system_value(ureg, TGSI_SEMANTIC_INSTANCEID, 0);
struct ureg_dst layer =
ureg_DECL_output(ureg, TGSI_SEMANTIC_LAYER, 0);
ureg_MOV(ureg, ureg_writemask(layer, TGSI_WRITEMASK_X),
ureg_scalar(instance_id, TGSI_SWIZZLE_X));
}
ureg_END(ureg);
*vs = ureg_create_shader_and_destroy(ureg, &sctx->b);
return *vs;
}
/* Create a compute shader implementing clear_buffer or copy_buffer. */
void *si_create_dma_compute_shader(struct pipe_context *ctx,
unsigned num_dwords_per_thread,
bool dst_stream_cache_policy, bool is_copy)
{
assert(util_is_power_of_two_nonzero(num_dwords_per_thread));
unsigned store_qualifier = TGSI_MEMORY_COHERENT | TGSI_MEMORY_RESTRICT;
if (dst_stream_cache_policy)
store_qualifier |= TGSI_MEMORY_STREAM_CACHE_POLICY;
/* Don't cache loads, because there is no reuse. */
unsigned load_qualifier = store_qualifier | TGSI_MEMORY_STREAM_CACHE_POLICY;
unsigned num_mem_ops = MAX2(1, num_dwords_per_thread / 4);
unsigned *inst_dwords = alloca(num_mem_ops * sizeof(unsigned));
for (unsigned i = 0; i < num_mem_ops; i++) {
if (i*4 < num_dwords_per_thread)
inst_dwords[i] = MIN2(4, num_dwords_per_thread - i*4);
}
struct ureg_program *ureg = ureg_create(PIPE_SHADER_COMPUTE);
if (!ureg)
return NULL;
ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH, 64);
ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT, 1);
ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH, 1);
struct ureg_src value;
if (!is_copy) {
ureg_property(ureg, TGSI_PROPERTY_CS_USER_DATA_DWORDS, inst_dwords[0]);
value = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_CS_USER_DATA, 0);
}
struct ureg_src tid = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_THREAD_ID, 0);
struct ureg_src blk = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_BLOCK_ID, 0);
struct ureg_dst store_addr = ureg_writemask(ureg_DECL_temporary(ureg), TGSI_WRITEMASK_X);
struct ureg_dst load_addr = ureg_writemask(ureg_DECL_temporary(ureg), TGSI_WRITEMASK_X);
struct ureg_dst dstbuf = ureg_dst(ureg_DECL_buffer(ureg, 0, false));
struct ureg_src srcbuf;
struct ureg_src *values = NULL;
if (is_copy) {
srcbuf = ureg_DECL_buffer(ureg, 1, false);
values = malloc(num_mem_ops * sizeof(struct ureg_src));
}
/* If there are multiple stores, the first store writes into 0+tid,
* the 2nd store writes into 64+tid, the 3rd store writes into 128+tid, etc.
*/
ureg_UMAD(ureg, store_addr, blk, ureg_imm1u(ureg, 64 * num_mem_ops), tid);
/* Convert from a "store size unit" into bytes. */
ureg_UMUL(ureg, store_addr, ureg_src(store_addr),
ureg_imm1u(ureg, 4 * inst_dwords[0]));
ureg_MOV(ureg, load_addr, ureg_src(store_addr));
/* Distance between a load and a store for latency hiding. */
unsigned load_store_distance = is_copy ? 8 : 0;
for (unsigned i = 0; i < num_mem_ops + load_store_distance; i++) {
int d = i - load_store_distance;
if (is_copy && i < num_mem_ops) {
if (i) {
ureg_UADD(ureg, load_addr, ureg_src(load_addr),
ureg_imm1u(ureg, 4 * inst_dwords[i] * 64));
}
values[i] = ureg_src(ureg_DECL_temporary(ureg));
struct ureg_dst dst =
ureg_writemask(ureg_dst(values[i]),
u_bit_consecutive(0, inst_dwords[i]));
struct ureg_src srcs[] = {srcbuf, ureg_src(load_addr)};
ureg_memory_insn(ureg, TGSI_OPCODE_LOAD, &dst, 1, srcs, 2,
load_qualifier, TGSI_TEXTURE_BUFFER, 0);
}
if (d >= 0) {
if (d) {
ureg_UADD(ureg, store_addr, ureg_src(store_addr),
ureg_imm1u(ureg, 4 * inst_dwords[d] * 64));
}
struct ureg_dst dst =
ureg_writemask(dstbuf, u_bit_consecutive(0, inst_dwords[d]));
struct ureg_src srcs[] =
{ureg_src(store_addr), is_copy ? values[d] : value};
ureg_memory_insn(ureg, TGSI_OPCODE_STORE, &dst, 1, srcs, 2,
store_qualifier, TGSI_TEXTURE_BUFFER, 0);
}
}
ureg_END(ureg);
struct pipe_compute_state state = {};
state.ir_type = PIPE_SHADER_IR_TGSI;
state.prog = ureg_get_tokens(ureg, NULL);
void *cs = ctx->create_compute_state(ctx, &state);
ureg_destroy(ureg);
free(values);
return cs;
}
static void *
create_fs(struct st_context *st, bool download, enum pipe_texture_target target)
{
struct pipe_context *pipe = st->pipe;
struct pipe_screen *screen = pipe->screen;
struct ureg_program *ureg;
bool have_layer;
struct ureg_dst out;
struct ureg_src sampler;
struct ureg_src pos;
struct ureg_src layer;
struct ureg_src const0;
struct ureg_src const1;
struct ureg_dst temp0;
have_layer =
st->pbo.layers &&
(!download || target == PIPE_TEXTURE_1D_ARRAY
|| target == PIPE_TEXTURE_2D_ARRAY
|| target == PIPE_TEXTURE_3D
|| target == PIPE_TEXTURE_CUBE
|| target == PIPE_TEXTURE_CUBE_ARRAY);
ureg = ureg_create(PIPE_SHADER_FRAGMENT);
if (!ureg)
return NULL;
if (!download) {
out = ureg_DECL_output(ureg, TGSI_SEMANTIC_COLOR, 0);
} else {
struct ureg_src image;
/* writeonly images do not require an explicitly given format. */
image = ureg_DECL_image(ureg, 0, TGSI_TEXTURE_BUFFER, PIPE_FORMAT_NONE,
true, false);
out = ureg_dst(image);
}
sampler = ureg_DECL_sampler(ureg, 0);
if (screen->get_param(screen, PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL)) {
pos = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_POSITION, 0);
} else {
pos = ureg_DECL_fs_input(ureg, TGSI_SEMANTIC_POSITION, 0,
TGSI_INTERPOLATE_LINEAR);
}
if (have_layer) {
layer = ureg_DECL_fs_input(ureg, TGSI_SEMANTIC_LAYER, 0,
TGSI_INTERPOLATE_CONSTANT);
}
const0 = ureg_DECL_constant(ureg, 0);
const1 = ureg_DECL_constant(ureg, 1);
temp0 = ureg_DECL_temporary(ureg);
/* Note: const0 = [ -xoffset + skip_pixels, -yoffset, stride, image_height ] */
/* temp0.xy = f2i(temp0.xy) */
ureg_F2I(ureg, ureg_writemask(temp0, TGSI_WRITEMASK_XY),
ureg_swizzle(pos,
TGSI_SWIZZLE_X, TGSI_SWIZZLE_Y,
TGSI_SWIZZLE_Y, TGSI_SWIZZLE_Y));
/* temp0.xy = temp0.xy + const0.xy */
ureg_UADD(ureg, ureg_writemask(temp0, TGSI_WRITEMASK_XY),
ureg_swizzle(ureg_src(temp0),
TGSI_SWIZZLE_X, TGSI_SWIZZLE_Y,
TGSI_SWIZZLE_Y, TGSI_SWIZZLE_Y),
ureg_swizzle(const0,
TGSI_SWIZZLE_X, TGSI_SWIZZLE_Y,
TGSI_SWIZZLE_Y, TGSI_SWIZZLE_Y));
/* temp0.x = const0.z * temp0.y + temp0.x */
ureg_UMAD(ureg, ureg_writemask(temp0, TGSI_WRITEMASK_X),
ureg_scalar(const0, TGSI_SWIZZLE_Z),
ureg_scalar(ureg_src(temp0), TGSI_SWIZZLE_Y),
ureg_scalar(ureg_src(temp0), TGSI_SWIZZLE_X));
if (have_layer) {
/* temp0.x = const0.w * layer + temp0.x */
ureg_UMAD(ureg, ureg_writemask(temp0, TGSI_WRITEMASK_X),
ureg_scalar(const0, TGSI_SWIZZLE_W),
ureg_scalar(layer, TGSI_SWIZZLE_X),
ureg_scalar(ureg_src(temp0), TGSI_SWIZZLE_X));
}
/* temp0.w = 0 */
ureg_MOV(ureg, ureg_writemask(temp0, TGSI_WRITEMASK_W), ureg_imm1u(ureg, 0));
if (download) {
struct ureg_dst temp1;
struct ureg_src op[2];
temp1 = ureg_DECL_temporary(ureg);
/* temp1.xy = pos.xy */
ureg_F2I(ureg, ureg_writemask(temp1, TGSI_WRITEMASK_XY), pos);
/* temp1.zw = 0 */
ureg_MOV(ureg, ureg_writemask(temp1, TGSI_WRITEMASK_ZW), ureg_imm1u(ureg, 0));
if (have_layer) {
struct ureg_dst temp1_layer =
ureg_writemask(temp1, target == PIPE_TEXTURE_1D_ARRAY ? TGSI_WRITEMASK_Y
: TGSI_WRITEMASK_Z);
/* temp1.y/z = layer */
ureg_MOV(ureg, temp1_layer, ureg_scalar(layer, TGSI_SWIZZLE_X));
if (target == PIPE_TEXTURE_3D) {
/* temp1.z += layer_offset */
ureg_UADD(ureg, temp1_layer,
ureg_scalar(ureg_src(temp1), TGSI_SWIZZLE_Z),
ureg_scalar(const1, TGSI_SWIZZLE_X));
}
}
/* temp1 = txf(sampler, temp1) */
ureg_TXF(ureg, temp1, util_pipe_tex_to_tgsi_tex(target, 1),
ureg_src(temp1), sampler);
/* store(out, temp0, temp1) */
op[0] = ureg_src(temp0);
op[1] = ureg_src(temp1);
ureg_memory_insn(ureg, TGSI_OPCODE_STORE, &out, 1, op, 2, 0,
TGSI_TEXTURE_BUFFER, PIPE_FORMAT_NONE);
ureg_release_temporary(ureg, temp1);
} else {
/* out = txf(sampler, temp0.x) */
ureg_TXF(ureg, out, TGSI_TEXTURE_BUFFER, ureg_src(temp0), sampler);
}
ureg_release_temporary(ureg, temp0);
ureg_END(ureg);
return ureg_create_shader_and_destroy(ureg, pipe);
}
