void vVDecWriteAVCFG(UINT32 u4VDecID, UINT32 u4Addr, UINT32 u4Val)
{
#if ((CONFIG_CHIP_VER_CURR >= CONFIG_CHIP_VER_MT8560))
u4VDecID = 0;
#endif
if (u4VDecID == 0)
{
vWriteReg(AVC_FG_REG_OFFSET0 + u4Addr, u4Val);
}
else
{
vWriteReg(AVC_FG_REG_OFFSET1 + u4Addr, u4Val);
}
}
void vVDecWriteAVCMV(UINT32 u4VDecID, UINT32 u4Addr, UINT32 u4Val)
{
#if ((CONFIG_CHIP_VER_CURR >= CONFIG_CHIP_VER_MT8560))
u4VDecID = 0;
#endif
if (u4VDecID == 0)
{
vWriteReg(AVC_MV_REG_OFFSET0 + u4Addr, u4Val);
vVDecSimDumpW(u4VDecID, AVC_MV_REG_OFFSET0, u4Addr, u4Val);
#ifdef VDEC_SIM_DUMP
//vVDecSimDump(u4VDecID, AVC_MV_REG_OFFSET0, u4Addr, u4Val);
#endif
}
else
{
vWriteReg(AVC_MV_REG_OFFSET1 + u4Addr, u4Val);
vVDecSimDumpW(u4VDecID, AVC_MV_REG_OFFSET1, u4Addr, u4Val);
#ifdef VDEC_SIM_DUMP
//vVDecSimDump(u4VDecID, AVC_MV_REG_OFFSET1, u4Addr, u4Val);
#endif
}
}
void vVP9RISCWrite_MC(UINT32 u4Addr, UINT32 u4Value, UINT32 u4CoreId )
{
UINT32 VP9_MC_BASE = 0;
if(u4CoreId == 0)
{
VP9_MC_BASE = MC_REG_OFFSET0;
}
else
{
VP9_MC_BASE = MC_REG_OFFSET1;
}
vWriteReg(VP9_MC_BASE + u4Addr*4, u4Value);
//DRV_WriteReg( MC_BASE , u4Addr*4 , u4Value);
SIM_PRINT(" RISCWrite_MC(%u, %-10u, %u); // 0x%08x\n", u4Addr, u4Value, u4CoreId, u4Value);
}
void vVP9RISCWrite_VDEC_TOP( UINT32 u4Addr, UINT32 u4Value, UINT32 u4CoreId)
{
UINT32 VP9_MISC_BASE = 0;
if(u4CoreId == CORE_0_ID)
{
VP9_MISC_BASE = 0xF6020000;
}
else // currently do not know core 1 settings
{
VP9_MISC_BASE = 0xF6020000;
}
vWriteReg(VP9_MISC_BASE + u4Addr*4, u4Value);
//DRV_WriteReg( MISC_BASE , u4Addr*4 , u4Value);
SIM_PRINT (" RISCWrite_VDEC_TOP(%u , %-10u, %u); // 0x%08x\n",u4Addr, u4Value, u4CoreId, u4Value);
}
void vVP9RISCWrite_PP(UINT32 u4Addr, UINT32 u4Value, UINT32 u4CoreId)
{
UINT32 VP9_PP_BASE = 0;
if(u4CoreId == CORE_0_ID)
{
VP9_PP_BASE = HEVC_PP_REG_OFFSET0;
}
else
{
//PP_BASE = HEVC_PP_REG_OFFSET1;
}
vWriteReg(VP9_PP_BASE + u4Addr*4, u4Value);
//DRV_WriteReg( PP_BASE , u4Addr*4 , u4Value);
SIM_PRINT(" RISCWrite_PP(%u, %-10u, %u); // 0x%08x\n", u4Addr, u4Value, u4CoreId, u4Value);
}
void vVDecWriteVP8VLD(UINT32 u4VDecID, UINT32 u4Addr, UINT32 u4Val, UINT32 u4BSID)
{
u4VDecID = 0;
if (u4VDecID == 0)
{
vWriteReg(VP8_VLD_REG_OFFSET0 + u4Addr, u4Val);
// printk("VP8Write(VP8VLD(0x%X) + 0x%X[%d])=0x%X\n",VP8_VLD_REG_OFFSET0,u4Addr,u4Addr>>2,u4Val);
#ifdef VP8_REG_DUMP
if (_fgVP8DumpReg)
{
printk("RISCWrite(`VP8_VLD_BASE + %d*4, 32'h%x); \n", u4Addr >> 2, u4Val);
}
#endif
#ifdef VDEC_SIM_DUMP
vVDecSimDump(u4VDecID, VP8_VLD_REG_OFFSET0, u4Addr, u4Val);
#endif
}
void vVP9RISCWrite_BS2(UINT32 u4Addr, UINT32 u4Value, UINT32 u4CoreId)
{
UINT32 VP9_BS2_BASE = 0;
if( u4CoreId == CORE_0_ID)
{
VP9_BS2_BASE = VDEC_BS2_OFFSET0;
}
else if( u4CoreId == 1)
{
//BS2_BASE = VDEC_BS2_OFFSET1;
}
else
{
//BS2_BASE = LAE_BS2_OFFSET0;
}
vWriteReg(VDEC_BS2_OFFSET0 + u4Addr*4, u4Value);
//DRV_WriteReg( BS2_BASE , u4Addr*4 , u4Value);
SIM_PRINT(" RISCWrite_BS2(%u, %-10u, %u); // 0x%08x\n", u4Addr, u4Value, u4CoreId, u4Value);
}
void vVP9RISCWrite_VP9_VLD(UINT32 u4Addr, UINT32 u4Value, UINT32 u4CoreId)
{
UINT32 VP9_VLD_BASE = 0;
if( u4CoreId == CORE_0_ID)
{
VP9_VLD_BASE = VP9_VLD_REG_OFFSET0;
}
else if(u4CoreId == CORE_1_ID)
{
//VLD_BASE = VP9_VLD_REG_OFFSET1;
}
else
{
//VLD_BASE = LAE_VP9_VLD_OFFSET0;
}
vWriteReg(VP9_VLD_REG_OFFSET0 + u4Addr*4, u4Value);
//DRV_WriteReg( VLD_BASE , u4Addr*4 , u4Value);
SIM_PRINT(" RISCWrite_VP9_VLD(%u, %-10u, %u); // 0x%08x\n", u4Addr, u4Value, u4CoreId, u4Value);
}
