/*
* uvaxIII_conf() is called by cpu_attach to do the cpu_specific setup.
*/
void
uvaxIII_conf()
{
int syssub = GETSYSSUBT(vax_siedata);
/*
* MicroVAX III: We map in memory error registers,
* cache control registers, SSC registers,
* interprocessor registers and cache diag space.
*/
ka650merr_ptr = (void *)vax_map_physmem(KA650_MERR, 1);
ka650cbd_ptr = (void *)vax_map_physmem(KA650_CBD, 1);
ka650ssc_ptr = (void *)vax_map_physmem(KA650_SSC, 3);
ka650ipcr_ptr = (void *)vax_map_physmem(KA650_IPCR, 1);
KA650_CACHE_ptr = (void *)vax_map_physmem(KA650_CACHE,
(KA650_CACHESIZE/VAX_NBPG));
printf("cpu: KA6%d%d, CVAX microcode rev %d Firmware rev %d\n",
syssub == VAX_SIE_KA640 ? 4 : 5,
syssub == VAX_SIE_KA655 ? 5 : 0,
(vax_cpudata & 0xff), GETFRMREV(vax_siedata));
ka650setcache(CACHEON);
if (ctob(physmem) > ka650merr_ptr->merr_qbmbr) {
printf("physmem(0x%x) > qbmbr(0x%x)\n",
ctob(physmem), (int)ka650merr_ptr->merr_qbmbr);
panic("qbus map unprotected");
}
if (mfpr(PR_TODR) == 0)
mtpr(1, PR_TODR);
}
void
ka48_conf()
{
char *cpuname;
switch((vax_siedata >> 8) & 0xFF) {
case VAX_STYP_45:
cpuname = "KA45";
break;
case VAX_STYP_48:
cpuname = "KA48";
break;
default:
cpuname = "Unknown SOC";
}
printf("cpu: %s\n", cpuname);
ka48_cpu = (void *)vax_map_physmem(VS_REGS, 1);
printf("cpu: turning on floating point chip\n");
mtpr(2, PR_ACCS); /* Enable floating points */
/*
* Setup parameters necessary to read time from clock chip.
*/
clk_adrshift = 1; /* Addressed at long's... */
clk_tweak = 2; /* ...and shift two */
clk_page = (short *)vax_map_physmem(VS_CLOCK, 1);
}
void
ledattach(struct device *parent, struct device *self, void *aux)
{
struct led_softc *sc = (void *)self;
#if VAX49 || VAX53 || VXT
vaddr_t pgva;
#endif
printf("\n");
switch (vax_boardtype) {
#if VAX46
case VAX_BTYP_46:
{
extern struct vs_cpu *ka46_cpu;
sc->sc_reg = (volatile u_short *)(&ka46_cpu->vc_diagdsp);
sc->sc_pat = led_pattern8;
}
break;
#endif
#if VAX48
case VAX_BTYP_48:
{
extern struct vs_cpu *ka48_cpu;
sc->sc_reg = (volatile u_short *)(&ka48_cpu->vc_diagdsp);
sc->sc_pat = led_pattern8;
}
break;
#endif
#if VAX49
case VAX_BTYP_49:
pgva = vax_map_physmem(0x25800000, 1);
sc->sc_reg = (volatile u_short *)(pgva + 4);
sc->sc_pat = led_pattern8;
break;
#endif
#if VAX53
case VAX_BTYP_1303:
pgva = vax_map_physmem(0x20140000, 1);
sc->sc_reg = (volatile u_short *)(pgva + 0x30);
sc->sc_pat = led_pattern4;
break;
#endif
#if VXT
case VAX_BTYP_VXT:
pgva = vax_map_physmem(0x200c1000, 1);
sc->sc_reg = (volatile u_short *)pgva;
sc->sc_pat = led_pattern8;
break;
#endif
}
sc->sc_patpos = sc->sc_pat;
timeout_set(&sc->sc_tmo, led_blink, sc);
led_blink(sc);
}
void
ka46_conf()
{
printf("cpu: KA46\n");
ka46_cpu = (void *)vax_map_physmem(VS_REGS, 1);
printf("cpu: turning on floating point chip\n");
mtpr(2, PR_ACCS); /* Enable floating points */
/*
* Setup parameters necessary to read time from clock chip.
*/
clk_adrshift = 1; /* Addressed at long's... */
clk_tweak = 2; /* ...and shift two */
clk_page = (short *)vax_map_physmem(VS_CLOCK, 1);
}
/*
* uvaxII_conf() is called by cpu_attach to do the cpu_specific setup.
*/
void
ka630_conf()
{
clk_adrshift = 0; /* Addressed at short's... */
clk_tweak = 0; /* ...and no shifting */
clk_page = (short *)vax_map_physmem((paddr_t)KA630CLK, 1);
uvaxIIcpu_ptr = (void *)vax_map_physmem(VS_REGS, 1);
/*
* Enable memory parity error detection and clear error bits.
*/
uvaxIIcpu_ptr->uvaxII_mser = (UVAXIIMSER_PEN | UVAXIIMSER_MERR |
UVAXIIMSER_LEB);
}
void
ka660_conf()
{
printf("cpu0: KA660, microcode Rev. %d\n", vax_cpudata & 0377);
cpmbx = (struct cpmbx *)vax_map_physmem(0x20140400, 1);
}
void
ka53_conf()
{
char *cpuname;
/* This initialises ISP, avoiding interrupt exceptions */
{volatile int *hej = (void *)mfpr(PR_ISP); *hej = *hej; hej[-1] = hej[-1];}
/* This vector (qbus related?) comes out of nowhere, ignore it for now */
scb_vecalloc(0x0, (void *)nullop, NULL, SCB_ISTACK, NULL);
cpmbx = (struct cpmbx *)vax_map_physmem(0x20140400, 1);
switch((vax_siedata >> 8) & 0xFF) {
case VAX_STYP_50:
cpuname = "KA50";
break;
case VAX_STYP_51:
cpuname = "KA51";
break;
case VAX_STYP_52:
cpuname = "KA52";
break;
case VAX_STYP_53:
cpuname = "KA53";
break;
default:
cpuname = "unknown NVAX";
}
printf("cpu0: %s, ucode rev %d\n", cpuname, vax_cpudata & 0xff);
}
int
smg_match(device_t parent, cfdata_t match, void *aux)
{
struct vsbus_attach_args * const va = aux;
volatile uint16_t *ccmd;
volatile uint16_t *cfgtst;
uint16_t tmp, tmp2;
if (vax_boardtype == VAX_BTYP_49 || vax_boardtype == VAX_BTYP_53)
return 0;
ccmd = (uint16_t *)va->va_addr;
cfgtst = (uint16_t *)vax_map_physmem(VS_CFGTST, 1);
/*
* Try to find the cursor chip by testing the flip-flop.
* If nonexistent, no glass tty.
*/
ccmd[0] = CUR_CMD_HSHI|CUR_CMD_FOPB;
DELAY(300000);
tmp = cfgtst[0];
ccmd[0] = CUR_CMD_TEST|CUR_CMD_HSHI;
DELAY(300000);
tmp2 = cfgtst[0];
vax_unmap_physmem((vaddr_t)cfgtst, 1);
if (tmp2 != tmp)
return 20; /* Using periodic interrupt */
else
return 0;
}
void
ubi_attach(device_t parent, device_t self, void *aux)
{
struct sbi_attach_args sa;
printf("\n");
sa.sa_base = (bus_addr_t)NEX730;
#define NEXPAGES (sizeof(struct nexus) / VAX_NBPG)
#if 0
/*
* Probe for memory, can be in the first 4 slots.
*/
for (sa.sa_nexnum = 0; sa.sa_nexnum < 4; sa.sa_nexnum++) {
sa.sa_ioh = vax_map_physmem(NEX730 +
sizeof(struct nexus) * sa.sa_nexnum, NEXPAGES);
if (badaddr((caddr_t)sa.sa_ioh, 4)) {
vax_unmap_physmem((vaddr_t)sa.sa_ioh, NEXPAGES);
} else {
sa.sa_type = NEX_MEM16;
config_found(self, (void*)&sa, ubi_print);
}
}
#endif
/* VAX 730 fixed configuration */
/* memory */
sa.sa_nexnum = 0;
sa.sa_ioh = vax_map_physmem((int)NEX730 +
sizeof(struct nexus) * sa.sa_nexnum, NEXPAGES);
sa.sa_type = NEX_MEM16;
config_found(self, (void*)&sa, ubi_print);
printf("\n");
/* generic UBA */
sa.sa_nexnum = 3;
sa.sa_ioh = vax_map_physmem((int)NEX730 +
sizeof(struct nexus) * sa.sa_nexnum, NEXPAGES);
sa.sa_type = NEX_UBA0;
config_found(self, (void*)&sa, ubi_print);
}
void
ka53_conf(void)
{
/* Don't ask why, but we seem to need this... */
volatile int *hej = (void *)mfpr(PR_ISP);
*hej = *hej;
hej[-1] = hej[-1];
cpmbx = (struct cpmbx *)vax_map_physmem(0x20140400, 1);
}
void
tcbus_attach(device_t parent, device_t self, void *aux)
{
struct vsbus_attach_args * const va = aux;
struct tcbus_softc * const sc = device_private(self);
struct tcbus_attach_args tba;
struct pte *pte;
const size_t nentries = 32768;
int error;
int i;
error = bus_space_map(va->va_memt, KA4x_TURBO, 0x10000,
BUS_SPACE_MAP_LINEAR, &sc->sc_memh);
if (error) {
aprint_error(": failed to map TC slot 0: %d\n", error);
return;
}
sc->sc_slots[0].tcs_addr = sc->sc_memh;
sc->sc_slots[0].tcs_cookie = sc;
tba.tba_speed = TC_SPEED_12_5_MHZ;
tba.tba_slots = sc->sc_slots;
tba.tba_nslots = 1;
tba.tba_intr_evcnt = tcbus_intr_evcnt;
tba.tba_intr_establish = tcbus_intr_establish;
tba.tba_intr_disestablish = tcbus_intr_disestablish;
tba.tba_get_dma_tag = tcbus_get_dma_tag;
vax_sgmap_dmatag_init(&sc->sc_dmatag, sc, nentries);
pte = (struct pte *) vax_map_physmem(KA4x_TURBOMAPS,
nentries * sizeof(pte[0]));
for (i = nentries; i > 0; )
((uint32_t *) pte)[--i] = 0;
sc->sc_dmatag._sgmap = &sc->sc_sgmap;
/*
* Initialize the SGMAP.
*/
vax_sgmap_init(&sc->sc_dmatag, &sc->sc_sgmap, "tc_sgmap",
sc->sc_dmatag._wbase, sc->sc_dmatag._wsize, pte, 0);
aprint_normal("\n");
aprint_verbose_dev(self, "32K entry DMA SGMAP at PA 0x%x (VA %p)\n",
KA4x_TURBOMAPS, pte);
tcbus_dmat = &sc->sc_dmatag;
/* XXX: why not config_found(9)?? */
tcattach(parent, self, &tba);
}
/*
* hdc_attach() probes for all possible devices
*/
void
hdcattach(device_t parent, device_t self, void *aux)
{
struct vsbus_attach_args * const va = aux;
struct hdcsoftc * const sc = device_private(self);
struct hdc_attach_args ha;
int status, i;
aprint_normal("\n");
sc->sc_dev = self;
/*
* Get interrupt vector, enable instrumentation.
*/
scb_vecalloc(va->va_cvec, hdcintr, sc, SCB_ISTACK, &sc->sc_intrcnt);
evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL,
device_xname(self), "intr");
sc->sc_regs = vax_map_physmem(va->va_paddr, 1);
sc->sc_dmabase = (void *)va->va_dmaaddr;
sc->sc_dmasize = va->va_dmasize;
sc->sc_intbit = va->va_maskno;
rd_dmasize = min(MAXPHYS, sc->sc_dmasize); /* Used in rd_minphys */
sc->sc_vd.vd_go = hdc_qstart;
sc->sc_vd.vd_arg = sc;
/*
* Reset controller.
*/
HDC_WCMD(DKC_CMD_RESET);
DELAY(1000);
status = HDC_RSTAT;
if (status != (DKC_ST_DONE|DKC_TC_SUCCESS)) {
aprint_error_dev(self, "RESET failed, status 0x%x\n", status);
return;
}
bufq_alloc(&sc->sc_q, "disksort", BUFQ_SORT_CYLINDER);
/*
* now probe for all possible hard drives
*/
for (i = 0; i < 4; i++) {
if (i == 2) /* Floppy, needs special handling */
continue;
HDC_WCMD(DKC_CMD_DRSELECT | i);
DELAY(1000);
status = HDC_RSTAT;
ha.ha_drive = i;
if ((status & DKC_ST_TERMCOD) == DKC_TC_SUCCESS)
config_found(self, (void *)&ha, hdcprint);
}
}
/*
* hdc_attach() probes for all possible devices
*/
void
hdcattach(struct device *parent, struct device *self, void *aux)
{
struct vsbus_attach_args *va = aux;
struct hdcsoftc *sc = (void *)self;
struct hdc_attach_args ha;
int status, i;
u = 0; /* !!! - GCC */
printf("\n");
/*
* Get interrupt vector, enable instrumentation.
*/
scb_vecalloc(va->va_cvec, hdcintr, sc, SCB_ISTACK, &sc->sc_intrcnt);
evcount_attach(&sc->sc_intrcnt, self->dv_xname, (void *)va->va_cvec);
sc->sc_regs = vax_map_physmem(va->va_paddr, 1);
sc->sc_dmabase = (caddr_t)va->va_dmaaddr;
sc->sc_dmasize = va->va_dmasize;
sc->sc_intbit = va->va_maskno;
hd_dmasize = min(MAXPHYS, sc->sc_dmasize); /* Used in hd_minphys */
sc->sc_vd.vd_go = hdc_qstart;
sc->sc_vd.vd_arg = sc;
/*
* Reset controller.
*/
HDC_WCMD(DKC_CMD_RESET);
DELAY(1000);
status = HDC_RSTAT;
if (status != (DKC_ST_DONE|DKC_TC_SUCCESS)) {
printf("%s: RESET failed, status 0x%x\n",
sc->sc_dev.dv_xname, status);
return;
}
/*
* now probe for all possible hard drives
*/
for (i = 0; i < 4; i++) {
if (i == 2) /* Floppy, needs special handling */
continue;
HDC_WCMD(DKC_CMD_DRSELECT | i);
DELAY(1000);
status = HDC_RSTAT;
ha.ha_drive = i;
if ((status & DKC_ST_TERMCOD) == DKC_TC_SUCCESS)
config_found(self, (void *)&ha, hdcprint);
}
}
void
ka410_conf()
{
struct vs_cpu *ka410_cpu;
ka410_cpu = (struct vs_cpu *)vax_map_physmem(VS_REGS, 1);
switch (vax_cputype) {
case VAX_TYP_UV2:
ka410_cpu->vc_410mser = 1;
printf("cpu: KA410\n");
break;
case VAX_TYP_CVAX:
printf("cpu: KA41/42\n");
ka410_cpu->vc_vdcorg = 0; /* XXX */
ka410_cpu->vc_parctl = PARCTL_CPEN | PARCTL_DPEN ;
printf("cpu: Enabling primary cache, ");
mtpr(KA420_CADR_S2E|KA420_CADR_S1E|KA420_CADR_ISE|KA420_CADR_DSE,
PR_CADR);
if (vax_confdata & KA420_CFG_CACHPR) {
l2cache = (void *)vax_map_physmem(KA420_CH2_BASE,
(KA420_CH2_SIZE / VAX_NBPG));
cacr = (void *)vax_map_physmem(KA420_CACR, 1);
printf("secondary cache\n");
ka41_cache_enable();
} else
printf("no secondary cache present\n");
}
/* Done with ka410_cpu - release it */
vax_unmap_physmem((vaddr_t)ka410_cpu, 1);
/*
* Setup parameters necessary to read time from clock chip.
*/
clk_adrshift = 1; /* Addressed at long's... */
clk_tweak = 2; /* ...and shift two */
clk_page = (short *)vax_map_physmem(KA420_WAT_BASE, 1);
}
void
ka410_conf(void)
{
struct cpu_info * const ci = curcpu();
struct vs_cpu *ka410_cpu;
ka410_cpu = (struct vs_cpu *)vax_map_physmem(VS_REGS, 1);
switch (vax_cputype) {
case VAX_TYP_UV2:
ka410_cpu->vc_410mser = 1;
ci->ci_cpustr = "KA410, UV2";
break;
case VAX_TYP_CVAX:
ka410_cpu->vc_vdcorg = 0; /* XXX */
ka410_cpu->vc_parctl = PARCTL_CPEN | PARCTL_DPEN ;
mtpr(KA420_CADR_S2E|KA420_CADR_S1E|KA420_CADR_ISE|KA420_CADR_DSE, PR_CADR);
if (vax_confdata & KA420_CFG_CACHPR) {
l2cache = (void *)vax_map_physmem(KA420_CH2_BASE,
(KA420_CH2_SIZE / VAX_NBPG));
cacr = (void *)vax_map_physmem(KA420_CACR, 1);
ka41_cache_enable();
ci->ci_cpustr =
"KA420, CVAX, 1KB L1 cache, 64KB L2 cache";
} else {
ci->ci_cpustr = "KA420, CVAX, 1KB L1 cache";
}
}
/* Done with ka410_cpu - release it */
vax_unmap_physmem((vaddr_t)ka410_cpu, 1);
/*
* Setup parameters necessary to read time from clock chip.
*/
clk_adrshift = 1; /* Addressed at long's... */
clk_tweak = 2; /* ...and shift two */
clk_page = (short *)vax_map_physmem(KA420_WAT_BASE, 1);
}
void
ka48_conf()
{
char *cpuname;
switch (vax_cpustype) {
case VAX_STYP_45:
cpuname = "KA45";
break;
case VAX_STYP_48:
cpuname = "KA48";
break;
default:
cpuname = "Unknown SOC";
}
printf("cpu: %s\n", cpuname);
ka48_cpu = (void *)vax_map_physmem(VS_REGS, 1);
/*
* Setup parameters necessary to read time from clock chip.
*/
clk_adrshift = 1; /* Addressed at long's... */
clk_tweak = 2; /* ...and shift two */
clk_page = (short *)vax_map_physmem(VS_CLOCK, 1);
}
void
smg_attach(device_t parent, device_t self, void *aux)
{
struct wsemuldisplaydev_attach_args aa;
struct wsdisplay_font *console_font;
int fcookie;
aprint_normal("\n");
sm_addr = (void *)vax_map_physmem(SMADDR, (SMSIZE/VAX_NBPG));
curaddr = (void *)vax_map_physmem(KA420_CUR_BASE, 1);
if (sm_addr == 0) {
aprint_error_dev(self, "Couldn't alloc graphics memory.\n");
return;
}
if (curscr == NULL)
callout_init(&smg_cursor_ch, 0);
curscr = &smg_conscreen;
aa.console = (vax_confdata & (KA420_CFG_L3CON|KA420_CFG_MULTU)) == 0;
aa.scrdata = &smg_screenlist;
aa.accessops = &smg_accessops;
callout_reset(&smg_cursor_ch, hz / 2, smg_crsr_blink, NULL);
curcmd = CUR_CMD_HSHI;
WRITECUR(CUR_CMD, curcmd);
if ((fcookie = wsfont_find(NULL, 8, 15, 0, WSDISPLAY_FONTORDER_R2L,
WSDISPLAY_FONTORDER_L2R, WSFONT_FIND_BITMAP)) < 0) {
aprint_error_dev(self, "could not find 8x15 font\n");
return;
}
if (wsfont_lock(fcookie, &console_font) != 0) {
aprint_error_dev(self, "could not lock 8x15 font\n");
return;
}
qf = console_font->data;
config_found(self, &aa, wsemuldisplaydevprint);
}
void
ka680_conf()
{
char *cpuname;
/* Don't ask why, but we seem to need this... */
volatile int *hej = (void *)mfpr(PR_ISP);
*hej = *hej;
hej[-1] = hej[-1];
cpmbx = (struct cpmbx *)vax_map_physmem(0x20140400, 1);
switch(vax_boardtype) {
case VAX_BTYP_1301:
switch((vax_siedata & 0xff00) >> 8) {
case VAX_STYP_675:
cpuname = "KA675";
break;
case VAX_STYP_680:
cpuname = "KA680";
break;
case VAX_STYP_690:
cpuname = "KA690";
break;
default:
cpuname = "unknown NVAX 1301";
}
break;
case VAX_BTYP_1305:
switch((vax_siedata & 0xff00) >> 8) {
case VAX_STYP_681:
cpuname = "KA681";
break;
case VAX_STYP_691:
cpuname = "KA691";
break;
case VAX_STYP_694:
if (vax_cpudata & 0x1000)
cpuname = "KA694";
else
cpuname = "KA692";
break;
default:
cpuname = "unknown NVAX 1305";
}
}
printf("cpu0: %s, ucode rev %d\n", cpuname, vax_cpudata & 0xff);
}
void
ka46_conf()
{
switch(vax_siedata & 0xFF) {
case VAX_VTYP_47:
printf("cpu: KA47\n");
break;
case VAX_VTYP_46:
printf("cpu: KA46\n");
break;
default:
printf("cpu: Unknown Mariah\n");
}
ka46_cpu = (void *)vax_map_physmem(VS_REGS, 1);
printf("cpu: turning on floating point chip\n");
mtpr(2, PR_ACCS); /* Enable floating points */
/*
* Setup parameters necessary to read time from clock chip.
*/
clk_adrshift = 1; /* Addressed at long's... */
clk_tweak = 2; /* ...and shift two */
clk_page = (short *)vax_map_physmem(VS_CLOCK, 1);
}
void
uba_dma_init(struct uba_vsoftc *sc)
{
bus_dma_tag_t t;
struct pte *pte;
/*
* Initialize the DMA tag used for sgmap-mapped DMA.
*/
t = &sc->uv_dmat;
t->_cookie = sc;
t->_wbase = 0;
t->_wsize = sc->uv_size;
t->_boundary = 0;
t->_sgmap = &sc->uv_sgmap;
t->_dmamap_create = uba_bus_dmamap_create_sgmap;
t->_dmamap_destroy = uba_bus_dmamap_destroy_sgmap;
t->_dmamap_load = uba_bus_dmamap_load_sgmap;
t->_dmamap_load_mbuf = uba_bus_dmamap_load_mbuf_sgmap;
t->_dmamap_load_uio = uba_bus_dmamap_load_uio_sgmap;
t->_dmamap_load_raw = uba_bus_dmamap_load_raw_sgmap;
t->_dmamap_unload = uba_bus_dmamap_unload_sgmap;
t->_dmamap_sync = uba_bus_dmamap_sync;
t->_dmamem_alloc = _bus_dmamem_alloc;
t->_dmamem_free = _bus_dmamem_free;
t->_dmamem_map = _bus_dmamem_map;
t->_dmamem_unmap = _bus_dmamem_unmap;
t->_dmamem_mmap = _bus_dmamem_mmap;
/*
* Map in Unibus map registers, if not mapped in already.
*/
if (sc->uv_uba) {
pte = sc->uv_uba->uba_map;
} else {
pte = (struct pte *)vax_map_physmem(sc->uv_addr,
vax_btoc(vax_btoc(sc->uv_size) * sizeof(struct pte)));
if (pte == 0)
panic("uba_dma_init");
}
/*
* Initialize the SGMAP.
*/
vax_sgmap_init(t, &sc->uv_sgmap, "uba_sgmap", 0, sc->uv_size, pte, 0);
}
void
ka49_conf()
{
printf("cpu0: KA49\n");
/* Why??? */
{ volatile int *hej = (void *)mfpr(PR_ISP); *hej = *hej; hej[-1] = hej[-1];}
/* This vector shows up during shutdown, ignore it for now. */
scb_vecalloc(0x0, (void *)nullop, NULL, SCB_ISTACK, NULL);
/*
* Setup parameters necessary to read time from clock chip.
*/
clk_adrshift = 1; /* Addressed at long's... */
clk_tweak = 2; /* ...and shift two */
clk_page = (short *)vax_map_physmem(0x25400000, 1);
}
static void
nmi_mainbus_attach(struct device *parent, struct device *self, void *aux)
{
struct nmi_attach_args na;
int nbia, *r = 0;
printf("\n");
/* One CPU is always found */
na.slot = 20;
config_found(self, (void *)&na, nmi_mainbus_print);
/* Check for a second one */
if (vax_boardtype == VAX_BTYP_8800) {
na.slot = 21;
config_found(self, (void *)&na, nmi_mainbus_print);
}
/* One memory adapter is also present */
na.slot = 10;
config_found(self, (void *)&na, nmi_mainbus_print);
/* Enable BI interrupts */
mtpr(NICTRL_DEV0|NICTRL_DEV1|NICTRL_MNF, PR_NICTRL);
/* Search for NBIA/NBIB adapters */
for (nbia = 0; nbia < 2; nbia++) {
if (r)
vax_unmap_physmem((vaddr_t)r, 1);
r = (int *)vax_map_physmem(NBIA_REGS(nbia), 1);
if (badaddr((caddr_t)r, 4))
continue;
na.slot = 2 * nbia;
if (r[1] & 2)
config_found(self, (void *)&na, nmi_mainbus_print);
na.slot++;
if (r[1] & 4)
config_found(self, (void *)&na, nmi_mainbus_print);
}
}
/*
* Interface exists: make available by filling in network interface
* record. System will initialize the interface when it is ready
* to accept packets.
*/
void
ze_mainbus_attach(device_t parent, device_t self, void *aux)
{
struct mainbus_attach_args * const ma = aux;
struct ze_softc * const sc = device_private(self);
const struct sgec_data * const sd = ze_find();
const uint32_t *ea;
size_t i;
int error;
sc->sc_dev = self;
/*
* Map in SGEC registers.
*/
sc->sc_dmat = ma->ma_dmat;
sc->sc_iot = ma->ma_iot;
sc->sc_intvec = sd->sd_intvec;
error = bus_space_map(sc->sc_iot, sd->sd_addr, PAGE_SIZE, 0,
&sc->sc_ioh);
if (error) {
aprint_error(": failed to map %#lx: %d\n", sd->sd_addr, error);
return;
}
/*
* Map in, read and release ethernet rom address.
*/
ea = (uint32_t *)vax_map_physmem(sd->sd_rom, 1);
for (i = 0; i < ETHER_ADDR_LEN; i++)
sc->sc_enaddr[i] = (ea[i] >> sd->sd_romshift) & 0377;
vax_unmap_physmem((vaddr_t)ea, 1);
scb_vecalloc(sc->sc_intvec, (void (*)(void *)) sgec_intr, sc,
SCB_ISTACK, &sc->sc_intrcnt);
sgec_attach(sc);
}
void
ka660_conf(void)
{
cpmbx = (struct cpmbx *)vax_map_physmem(0x20140400, 1);
}
void
le_fwio_attach(struct device *parent, struct device *self, void *aux)
{
struct fwio_attach_args *faa = (struct fwio_attach_args *)aux;
struct le_fwio_softc *lsc = (struct le_fwio_softc *)self;
struct lance_softc *sc = &lsc->sc_am7990.lsc;
unsigned int vec;
uint32_t *esar;
int i;
vec = faa->faa_vecbase + FBIC_DEVIRQ1 * 4;
printf(" vec %d", vec);
/*
* Map registers.
*/
lsc->sc_rdp = (volatile uint16_t *)
vax_map_physmem(faa->faa_base + FWIO_LANCE_REG_OFFSET, 1);
lsc->sc_rap = lsc->sc_rdp + 2;
/*
* Register access functions.
*/
sc->sc_rdcsr = le_fwio_rdcsr;
sc->sc_wrcsr = le_fwio_wrcsr;
/*
* Map buffers.
*/
sc->sc_mem = (void *)uvm_km_valloc(kernel_map, FWIO_LANCE_BUF_SIZE);
if (sc->sc_mem == NULL) {
vax_unmap_physmem(faa->faa_base + FWIO_LANCE_REG_OFFSET, 1);
printf(": can't map buffers\n");
return;
}
ioaccess((vaddr_t)sc->sc_mem, faa->faa_base +
FWIO_LANCE_BUF_OFFSET, FWIO_LANCE_BUF_SIZE >> VAX_PGSHIFT);
sc->sc_addr = FWIO_LANCE_BUF_OFFSET;
sc->sc_memsize = FWIO_LANCE_BUF_SIZE;
sc->sc_conf3 = 0;
sc->sc_copytodesc = lance_copytobuf_contig;
sc->sc_copyfromdesc = lance_copyfrombuf_contig;
sc->sc_copytobuf = lance_copytobuf_contig;
sc->sc_copyfrombuf = lance_copyfrombuf_contig;
sc->sc_zerobuf = lance_zerobuf_contig;
/*
* Get the Ethernet address from the Station Address ROM.
*/
esar = (uint32_t *)vax_map_physmem(faa->faa_base + FWIO_ESAR_OFFSET, 1);
for (i = 0; i < 6; i++)
sc->sc_arpcom.ac_enaddr[i] =
(esar[i] & FWIO_ESAR_MASK) >> FWIO_ESAR_SHIFT;
vax_unmap_physmem((vaddr_t)esar, 1);
/*
* Register interrupt handler.
*/
if (mbus_intr_establish(vec, IPL_NET, le_fwio_intr, sc,
self->dv_xname) != 0) {
vax_unmap_physmem(faa->faa_base + FWIO_LANCE_REG_OFFSET, 1);
uvm_km_free(kernel_map, (vaddr_t)sc->sc_mem,
FWIO_LANCE_BUF_SIZE);
printf(": can't establish interrupt\n");
return;
}
/*
* Complete attachment.
*/
am7990_config(&lsc->sc_am7990);
}
void
legss_attach(struct device *parent, struct device *self, void *aux)
{
struct legss_softc *sc = (struct legss_softc *)self;
struct legss_screen *scr;
struct wsemuldisplaydev_attach_args aa;
int console;
vaddr_t tmp;
extern struct consdev wsdisplay_cons;
console = (vax_confdata & 0x60) != 0 && cn_tab == &wsdisplay_cons;
if (console) {
scr = &legss_consscr;
sc->sc_nscreens = 1;
} else {
scr = malloc(sizeof(struct legss_screen), M_DEVBUF, M_NOWAIT);
if (scr == NULL) {
printf(": can not allocate memory\n");
return;
}
tmp = vax_map_physmem(LEGSS_BASE + LEGSS_VRAM_OFFSET, 1);
if (tmp == 0L) {
printf(": can not probe depth\n");
goto bad1;
}
scr->ss_depth = legss_probe_depth(tmp);
vax_unmap_physmem(tmp, 1);
if (scr->ss_depth == 0) {
printf(": unrecognized depth\n");
goto bad1;
}
scr->ss_vram = vax_map_physmem(LEGSS_BASE + LEGSS_VRAM_OFFSET,
(LEGSS_VISHEIGHT * LEGSS_WIDTH * 32 / NBBY) / VAX_NBPG);
if (scr->ss_vram == 0L) {
printf(": can not map frame buffer\n");
goto bad1;
}
if (legss_setup_screen(scr) != 0) {
printf(": initialization failed\n");
goto bad2;
}
}
sc->sc_scr = scr;
printf(": %dx%d %d plane color framebuffer\n",
LEGSS_VISWIDTH, LEGSS_VISHEIGHT, scr->ss_depth);
aa.console = console;
aa.scrdata = &legss_screenlist;
aa.accessops = &legss_accessops;
aa.accesscookie = sc;
aa.defaultscreens = 0;
config_found(self, &aa, wsemuldisplaydevprint);
return;
bad2:
vax_unmap_physmem(scr->ss_vram,
(LEGSS_VISHEIGHT * LEGSS_WIDTH * 32 / NBBY) / VAX_NBPG);
bad1:
free(scr, M_DEVBUF);
}
