static void
vc4_context_destroy(struct pipe_context *pctx)
{
struct vc4_context *vc4 = vc4_context(pctx);
if (vc4->blitter)
util_blitter_destroy(vc4->blitter);
if (vc4->primconvert)
util_primconvert_destroy(vc4->primconvert);
if (vc4->uploader)
u_upload_destroy(vc4->uploader);
util_slab_destroy(&vc4->transfer_pool);
pipe_surface_reference(&vc4->framebuffer.cbufs[0], NULL);
pipe_surface_reference(&vc4->framebuffer.zsbuf, NULL);
vc4_bo_unreference(&vc4->tile_alloc);
vc4_bo_unreference(&vc4->tile_state);
vc4_program_fini(pctx);
ralloc_free(vc4);
}
void
vc4_job_reset(struct vc4_context *vc4)
{
struct vc4_bo **referenced_bos = vc4->bo_pointers.base;
for (int i = 0; i < cl_offset(&vc4->bo_handles) / 4; i++) {
vc4_bo_unreference(&referenced_bos[i]);
}
vc4_reset_cl(&vc4->bcl);
vc4_reset_cl(&vc4->shader_rec);
vc4_reset_cl(&vc4->uniforms);
vc4_reset_cl(&vc4->bo_handles);
vc4_reset_cl(&vc4->bo_pointers);
vc4->shader_rec_count = 0;
vc4->needs_flush = false;
vc4->draw_calls_queued = 0;
/* We have no hardware context saved between our draw calls, so we
* need to flag the next draw as needing all state emitted. Emitting
* all state at the start of our draws is also what ensures that we
* return to the state we need after a previous tile has finished.
*/
vc4->dirty = ~0;
vc4->resolve = 0;
vc4->cleared = 0;
vc4->draw_min_x = ~0;
vc4->draw_min_y = ~0;
vc4->draw_max_x = 0;
vc4->draw_max_y = 0;
}
void
vc4_flush(struct pipe_context *pctx)
{
struct vc4_context *vc4 = vc4_context(pctx);
if (!vc4->needs_flush)
return;
cl_u8(&vc4->bcl, VC4_PACKET_FLUSH_ALL);
cl_u8(&vc4->bcl, VC4_PACKET_NOP);
cl_u8(&vc4->bcl, VC4_PACKET_HALT);
vc4_setup_rcl(vc4);
struct drm_vc4_submit_cl submit;
memset(&submit, 0, sizeof(submit));
submit.bo_handles = vc4->bo_handles.base;
submit.bo_handle_count = (vc4->bo_handles.next -
vc4->bo_handles.base) / 4;
submit.bin_cl = vc4->bcl.base;
submit.bin_cl_size = vc4->bcl.next - vc4->bcl.base;
submit.render_cl = vc4->rcl.base;
submit.render_cl_size = vc4->rcl.next - vc4->rcl.base;
submit.shader_rec = vc4->shader_rec.base;
submit.shader_rec_size = vc4->shader_rec.next - vc4->shader_rec.base;
submit.shader_rec_count = vc4->shader_rec_count;
submit.uniforms = vc4->uniforms.base;
submit.uniforms_size = vc4->uniforms.next - vc4->uniforms.base;
if (!(vc4_debug & VC4_DEBUG_NORAST)) {
int ret;
#ifndef USE_VC4_SIMULATOR
ret = drmIoctl(vc4->fd, DRM_IOCTL_VC4_SUBMIT_CL, &submit);
#else
ret = vc4_simulator_flush(vc4, &submit);
#endif
if (ret)
errx(1, "VC4 submit failed\n");
}
vc4_reset_cl(&vc4->bcl);
vc4_reset_cl(&vc4->rcl);
vc4_reset_cl(&vc4->shader_rec);
vc4_reset_cl(&vc4->uniforms);
vc4_reset_cl(&vc4->bo_handles);
struct vc4_bo **referenced_bos = vc4->bo_pointers.base;
for (int i = 0; i < submit.bo_handle_count; i++)
vc4_bo_unreference(&referenced_bos[i]);
vc4_reset_cl(&vc4->bo_pointers);
vc4->shader_rec_count = 0;
vc4->needs_flush = false;
vc4->draw_call_queued = false;
vc4->dirty = ~0;
vc4->resolve = 0;
vc4->cleared = 0;
}
static void
vc4_resource_destroy(struct pipe_screen *pscreen,
struct pipe_resource *prsc)
{
struct vc4_resource *rsc = vc4_resource(prsc);
pipe_resource_reference(&rsc->shadow_parent, NULL);
vc4_bo_unreference(&rsc->bo);
free(rsc);
}
static void
vc4_resource_bo_alloc(struct vc4_resource *rsc)
{
struct pipe_resource *prsc = &rsc->base.b;
struct pipe_screen *pscreen = prsc->screen;
vc4_bo_unreference(&rsc->bo);
rsc->bo = vc4_bo_alloc(vc4_screen(pscreen),
rsc->slices[0].offset +
rsc->slices[0].size +
rsc->cube_map_stride * (prsc->array_size - 1),
"resource");
}
static void
vc4_emit_gl_shader_state(struct vc4_context *vc4, const struct pipe_draw_info *info)
{
/* VC4_DIRTY_VTXSTATE */
struct vc4_vertex_stateobj *vtx = vc4->vtx;
/* VC4_DIRTY_VTXBUF */
struct vc4_vertexbuf_stateobj *vertexbuf = &vc4->vertexbuf;
/* The simulator throws a fit if VS or CS don't read an attribute, so
* we emit a dummy read.
*/
uint32_t num_elements_emit = MAX2(vtx->num_elements, 1);
/* Emit the shader record. */
struct vc4_cl_out *shader_rec =
cl_start_shader_reloc(&vc4->shader_rec, 3 + num_elements_emit);
/* VC4_DIRTY_PRIM_MODE | VC4_DIRTY_RASTERIZER */
cl_u16(&shader_rec,
VC4_SHADER_FLAG_ENABLE_CLIPPING |
VC4_SHADER_FLAG_FS_SINGLE_THREAD |
((info->mode == PIPE_PRIM_POINTS &&
vc4->rasterizer->base.point_size_per_vertex) ?
VC4_SHADER_FLAG_VS_POINT_SIZE : 0));
/* VC4_DIRTY_COMPILED_FS */
cl_u8(&shader_rec, 0); /* fs num uniforms (unused) */
cl_u8(&shader_rec, vc4->prog.fs->num_inputs);
cl_reloc(vc4, &vc4->shader_rec, &shader_rec, vc4->prog.fs->bo, 0);
cl_u32(&shader_rec, 0); /* UBO offset written by kernel */
/* VC4_DIRTY_COMPILED_VS */
cl_u16(&shader_rec, 0); /* vs num uniforms */
cl_u8(&shader_rec, vc4->prog.vs->vattrs_live);
cl_u8(&shader_rec, vc4->prog.vs->vattr_offsets[8]);
cl_reloc(vc4, &vc4->shader_rec, &shader_rec, vc4->prog.vs->bo, 0);
cl_u32(&shader_rec, 0); /* UBO offset written by kernel */
/* VC4_DIRTY_COMPILED_CS */
cl_u16(&shader_rec, 0); /* cs num uniforms */
cl_u8(&shader_rec, vc4->prog.cs->vattrs_live);
cl_u8(&shader_rec, vc4->prog.cs->vattr_offsets[8]);
cl_reloc(vc4, &vc4->shader_rec, &shader_rec, vc4->prog.cs->bo, 0);
cl_u32(&shader_rec, 0); /* UBO offset written by kernel */
uint32_t max_index = 0xffff;
for (int i = 0; i < vtx->num_elements; i++) {
struct pipe_vertex_element *elem = &vtx->pipe[i];
struct pipe_vertex_buffer *vb =
&vertexbuf->vb[elem->vertex_buffer_index];
struct vc4_resource *rsc = vc4_resource(vb->buffer);
/* not vc4->dirty tracked: vc4->last_index_bias */
uint32_t offset = (vb->buffer_offset +
elem->src_offset +
vb->stride * info->index_bias);
uint32_t vb_size = rsc->bo->size - offset;
uint32_t elem_size =
util_format_get_blocksize(elem->src_format);
cl_reloc(vc4, &vc4->shader_rec, &shader_rec, rsc->bo, offset);
cl_u8(&shader_rec, elem_size - 1);
cl_u8(&shader_rec, vb->stride);
cl_u8(&shader_rec, vc4->prog.vs->vattr_offsets[i]);
cl_u8(&shader_rec, vc4->prog.cs->vattr_offsets[i]);
if (vb->stride > 0) {
max_index = MIN2(max_index,
(vb_size - elem_size) / vb->stride);
}
}
if (vtx->num_elements == 0) {
assert(num_elements_emit == 1);
struct vc4_bo *bo = vc4_bo_alloc(vc4->screen, 4096, "scratch VBO");
cl_reloc(vc4, &vc4->shader_rec, &shader_rec, bo, 0);
cl_u8(&shader_rec, 16 - 1); /* element size */
cl_u8(&shader_rec, 0); /* stride */
cl_u8(&shader_rec, 0); /* VS VPM offset */
cl_u8(&shader_rec, 0); /* CS VPM offset */
vc4_bo_unreference(&bo);
}
cl_end(&vc4->shader_rec, shader_rec);
struct vc4_cl_out *bcl = cl_start(&vc4->bcl);
/* the actual draw call. */
cl_u8(&bcl, VC4_PACKET_GL_SHADER_STATE);
assert(vtx->num_elements <= 8);
/* Note that number of attributes == 0 in the packet means 8
* attributes. This field also contains the offset into shader_rec.
*/
cl_u32(&bcl, num_elements_emit & 0x7);
cl_end(&vc4->bcl, bcl);
vc4_write_uniforms(vc4, vc4->prog.fs,
&vc4->constbuf[PIPE_SHADER_FRAGMENT],
&vc4->fragtex);
vc4_write_uniforms(vc4, vc4->prog.vs,
&vc4->constbuf[PIPE_SHADER_VERTEX],
&vc4->verttex);
vc4_write_uniforms(vc4, vc4->prog.cs,
&vc4->constbuf[PIPE_SHADER_VERTEX],
&vc4->verttex);
vc4->last_index_bias = info->index_bias;
vc4->max_index = max_index;
}
int
vc4_simulator_flush(struct vc4_context *vc4, struct drm_vc4_submit_cl *args)
{
struct vc4_screen *screen = vc4->screen;
struct vc4_surface *csurf = vc4_surface(vc4->framebuffer.cbufs[0]);
struct vc4_resource *ctex = csurf ? vc4_resource(csurf->base.texture) : NULL;
uint32_t winsys_stride = ctex ? ctex->bo->simulator_winsys_stride : 0;
uint32_t sim_stride = ctex ? ctex->slices[0].stride : 0;
uint32_t row_len = MIN2(sim_stride, winsys_stride);
struct exec_info exec;
struct drm_device local_dev = {
.vc4 = vc4,
.simulator_mem_next = OVERFLOW_SIZE,
};
struct drm_device *dev = &local_dev;
int ret;
memset(&exec, 0, sizeof(exec));
if (ctex && ctex->bo->simulator_winsys_map) {
#if 0
fprintf(stderr, "%dx%d %d %d %d\n",
ctex->base.b.width0, ctex->base.b.height0,
winsys_stride,
sim_stride,
ctex->bo->size);
#endif
for (int y = 0; y < ctex->base.b.height0; y++) {
memcpy(ctex->bo->map + y * sim_stride,
ctex->bo->simulator_winsys_map + y * winsys_stride,
row_len);
}
}
exec.args = args;
ret = vc4_simulator_pin_bos(dev, &exec);
if (ret)
return ret;
ret = vc4_cl_validate(dev, &exec);
if (ret)
return ret;
int bfc = simpenrose_do_binning(exec.ct0ca, exec.ct0ea);
if (bfc != 1) {
fprintf(stderr, "Binning returned %d flushes, should be 1.\n",
bfc);
fprintf(stderr, "Relocated binning command list:\n");
vc4_dump_cl(screen->simulator_mem_base + exec.ct0ca,
exec.ct0ea - exec.ct0ca, false);
abort();
}
int rfc = simpenrose_do_rendering(exec.ct1ca, exec.ct1ea);
if (rfc != 1) {
fprintf(stderr, "Rendering returned %d frames, should be 1.\n",
rfc);
fprintf(stderr, "Relocated render command list:\n");
vc4_dump_cl(screen->simulator_mem_base + exec.ct1ca,
exec.ct1ea - exec.ct1ca, true);
abort();
}
ret = vc4_simulator_unpin_bos(&exec);
if (ret)
return ret;
vc4_bo_unreference(&exec.exec_bo->bo);
free(exec.exec_bo);
if (ctex && ctex->bo->simulator_winsys_map) {
for (int y = 0; y < ctex->base.b.height0; y++) {
memcpy(ctex->bo->simulator_winsys_map + y * winsys_stride,
ctex->bo->map + y * sim_stride,
row_len);
}
}
return 0;
}
void
vc4_flush(struct pipe_context *pctx)
{
struct vc4_context *vc4 = vc4_context(pctx);
if (!vc4->needs_flush)
return;
/* The FLUSH caps all of our bin lists with a VC4_PACKET_RETURN. */
cl_u8(&vc4->bcl, VC4_PACKET_FLUSH);
cl_u8(&vc4->bcl, VC4_PACKET_NOP);
cl_u8(&vc4->bcl, VC4_PACKET_HALT);
vc4_setup_rcl(vc4);
if (vc4_debug & VC4_DEBUG_CL) {
fprintf(stderr, "BCL:\n");
vc4_dump_cl(vc4->bcl.base, vc4->bcl.end - vc4->bcl.base, false);
fprintf(stderr, "RCL:\n");
vc4_dump_cl(vc4->rcl.base, vc4->rcl.end - vc4->rcl.base, true);
}
struct drm_vc4_submit_cl submit;
memset(&submit, 0, sizeof(submit));
submit.bo_handles = vc4->bo_handles.base;
submit.bo_handle_count = (vc4->bo_handles.next -
vc4->bo_handles.base) / 4;
submit.bin_cl = vc4->bcl.base;
submit.bin_cl_size = vc4->bcl.next - vc4->bcl.base;
submit.render_cl = vc4->rcl.base;
submit.render_cl_size = vc4->rcl.next - vc4->rcl.base;
submit.shader_rec = vc4->shader_rec.base;
submit.shader_rec_size = vc4->shader_rec.next - vc4->shader_rec.base;
submit.shader_rec_count = vc4->shader_rec_count;
submit.uniforms = vc4->uniforms.base;
submit.uniforms_size = vc4->uniforms.next - vc4->uniforms.base;
if (!(vc4_debug & VC4_DEBUG_NORAST)) {
int ret;
#ifndef USE_VC4_SIMULATOR
ret = drmIoctl(vc4->fd, DRM_IOCTL_VC4_SUBMIT_CL, &submit);
#else
ret = vc4_simulator_flush(vc4, &submit);
#endif
if (ret) {
fprintf(stderr, "VC4 submit failed\n");
abort();
}
}
vc4_reset_cl(&vc4->bcl);
vc4_reset_cl(&vc4->rcl);
vc4_reset_cl(&vc4->shader_rec);
vc4_reset_cl(&vc4->uniforms);
vc4_reset_cl(&vc4->bo_handles);
struct vc4_bo **referenced_bos = vc4->bo_pointers.base;
for (int i = 0; i < submit.bo_handle_count; i++)
vc4_bo_unreference(&referenced_bos[i]);
vc4_reset_cl(&vc4->bo_pointers);
vc4->shader_rec_count = 0;
vc4->needs_flush = false;
vc4->draw_call_queued = false;
/* We have no hardware context saved between our draw calls, so we
* need to flag the next draw as needing all state emitted. Emitting
* all state at the start of our draws is also what ensures that we
* return to the state we need after a previous tile has finished.
*/
vc4->dirty = ~0;
vc4->resolve = 0;
vc4->cleared = 0;
}
/**
* Does the initial bining command list setup for drawing to a given FBO.
*/
static void
vc4_start_draw(struct vc4_context *vc4)
{
if (vc4->needs_flush)
return;
uint32_t width = vc4->framebuffer.width;
uint32_t height = vc4->framebuffer.height;
uint32_t tilew = align(width, 64) / 64;
uint32_t tileh = align(height, 64) / 64;
/* Tile alloc memory setup: We use an initial alloc size of 32b. The
* hardware then aligns that to 256b (we use 4096, because all of our
* BO allocations align to that anyway), then for some reason the
* simulator wants an extra page available, even if you have overflow
* memory set up.
*/
uint32_t tile_alloc_size = 32 * tilew * tileh;
tile_alloc_size = align(tile_alloc_size, 4096);
tile_alloc_size += 4096;
uint32_t tile_state_size = 48 * tilew * tileh;
if (!vc4->tile_alloc || vc4->tile_alloc->size < tile_alloc_size) {
vc4_bo_unreference(&vc4->tile_alloc);
vc4->tile_alloc = vc4_bo_alloc(vc4->screen, tile_alloc_size,
"tile_alloc");
}
if (!vc4->tile_state || vc4->tile_state->size < tile_state_size) {
vc4_bo_unreference(&vc4->tile_state);
vc4->tile_state = vc4_bo_alloc(vc4->screen, tile_state_size,
"tile_state");
}
// Tile state data is 48 bytes per tile, I think it can be thrown away
// as soon as binning is finished.
cl_start_reloc(&vc4->bcl, 2);
cl_u8(&vc4->bcl, VC4_PACKET_TILE_BINNING_MODE_CONFIG);
cl_reloc(vc4, &vc4->bcl, vc4->tile_alloc, 0);
cl_u32(&vc4->bcl, vc4->tile_alloc->size);
cl_reloc(vc4, &vc4->bcl, vc4->tile_state, 0);
cl_u8(&vc4->bcl, tilew);
cl_u8(&vc4->bcl, tileh);
cl_u8(&vc4->bcl,
VC4_BIN_CONFIG_AUTO_INIT_TSDA |
VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_32 |
VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_32);
/* START_TILE_BINNING resets the statechange counters in the hardware,
* which are what is used when a primitive is binned to a tile to
* figure out what new state packets need to be written to that tile's
* command list.
*/
cl_u8(&vc4->bcl, VC4_PACKET_START_TILE_BINNING);
/* Reset the current compressed primitives format. This gets modified
* by VC4_PACKET_GL_INDEXED_PRIMITIVE and
* VC4_PACKET_GL_ARRAY_PRIMITIVE, so it needs to be reset at the start
* of every tile.
*/
cl_u8(&vc4->bcl, VC4_PACKET_PRIMITIVE_LIST_FORMAT);
cl_u8(&vc4->bcl, (VC4_PRIMITIVE_LIST_FORMAT_16_INDEX |
VC4_PRIMITIVE_LIST_FORMAT_TYPE_TRIANGLES));
vc4->needs_flush = true;
vc4->draw_call_queued = true;
}
static void
vc4_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
{
struct vc4_context *vc4 = vc4_context(pctx);
if (info->mode >= PIPE_PRIM_QUADS) {
util_primconvert_save_index_buffer(vc4->primconvert, &vc4->indexbuf);
util_primconvert_save_rasterizer_state(vc4->primconvert, &vc4->rasterizer->base);
util_primconvert_draw_vbo(vc4->primconvert, info);
return;
}
struct vc4_vertex_stateobj *vtx = vc4->vtx;
struct vc4_vertexbuf_stateobj *vertexbuf = &vc4->vertexbuf;
if (vc4->prim_mode != info->mode) {
vc4->prim_mode = info->mode;
vc4->dirty |= VC4_DIRTY_PRIM_MODE;
}
vc4_start_draw(vc4);
vc4_update_compiled_shaders(vc4, info->mode);
vc4_emit_state(pctx);
vc4->dirty = 0;
vc4_write_uniforms(vc4, vc4->prog.fs,
&vc4->constbuf[PIPE_SHADER_FRAGMENT],
&vc4->fragtex);
vc4_write_uniforms(vc4, vc4->prog.vs,
&vc4->constbuf[PIPE_SHADER_VERTEX],
&vc4->verttex);
vc4_write_uniforms(vc4, vc4->prog.cs,
&vc4->constbuf[PIPE_SHADER_VERTEX],
&vc4->verttex);
/* The simulator throws a fit if VS or CS don't read an attribute, so
* we emit a dummy read.
*/
uint32_t num_elements_emit = MAX2(vtx->num_elements, 1);
/* Emit the shader record. */
cl_start_shader_reloc(&vc4->shader_rec, 3 + num_elements_emit);
cl_u16(&vc4->shader_rec,
VC4_SHADER_FLAG_ENABLE_CLIPPING |
((info->mode == PIPE_PRIM_POINTS &&
vc4->rasterizer->base.point_size_per_vertex) ?
VC4_SHADER_FLAG_VS_POINT_SIZE : 0));
cl_u8(&vc4->shader_rec, 0); /* fs num uniforms (unused) */
cl_u8(&vc4->shader_rec, vc4->prog.fs->num_inputs);
cl_reloc(vc4, &vc4->shader_rec, vc4->prog.fs->bo, 0);
cl_u32(&vc4->shader_rec, 0); /* UBO offset written by kernel */
cl_u16(&vc4->shader_rec, 0); /* vs num uniforms */
cl_u8(&vc4->shader_rec, (1 << num_elements_emit) - 1); /* vs attribute array bitfield */
cl_u8(&vc4->shader_rec, 16 * num_elements_emit); /* vs total attribute size */
cl_reloc(vc4, &vc4->shader_rec, vc4->prog.vs->bo, 0);
cl_u32(&vc4->shader_rec, 0); /* UBO offset written by kernel */
cl_u16(&vc4->shader_rec, 0); /* cs num uniforms */
cl_u8(&vc4->shader_rec, (1 << num_elements_emit) - 1); /* cs attribute array bitfield */
cl_u8(&vc4->shader_rec, 16 * num_elements_emit); /* cs total attribute size */
cl_reloc(vc4, &vc4->shader_rec, vc4->prog.cs->bo, 0);
cl_u32(&vc4->shader_rec, 0); /* UBO offset written by kernel */
uint32_t max_index = 0xffff;
for (int i = 0; i < vtx->num_elements; i++) {
struct pipe_vertex_element *elem = &vtx->pipe[i];
struct pipe_vertex_buffer *vb =
&vertexbuf->vb[elem->vertex_buffer_index];
struct vc4_resource *rsc = vc4_resource(vb->buffer);
uint32_t offset = vb->buffer_offset + elem->src_offset;
uint32_t vb_size = rsc->bo->size - offset;
uint32_t elem_size =
util_format_get_blocksize(elem->src_format);
cl_reloc(vc4, &vc4->shader_rec, rsc->bo, offset);
cl_u8(&vc4->shader_rec, elem_size - 1);
cl_u8(&vc4->shader_rec, vb->stride);
cl_u8(&vc4->shader_rec, i * 16); /* VS VPM offset */
cl_u8(&vc4->shader_rec, i * 16); /* CS VPM offset */
if (vb->stride > 0) {
max_index = MIN2(max_index,
(vb_size - elem_size) / vb->stride);
}
}
if (vtx->num_elements == 0) {
assert(num_elements_emit == 1);
struct vc4_bo *bo = vc4_bo_alloc(vc4->screen, 4096, "scratch VBO");
cl_reloc(vc4, &vc4->shader_rec, bo, 0);
cl_u8(&vc4->shader_rec, 16 - 1); /* element size */
cl_u8(&vc4->shader_rec, 0); /* stride */
cl_u8(&vc4->shader_rec, 0); /* VS VPM offset */
cl_u8(&vc4->shader_rec, 0); /* CS VPM offset */
vc4_bo_unreference(&bo);
}
/* the actual draw call. */
cl_u8(&vc4->bcl, VC4_PACKET_GL_SHADER_STATE);
assert(vtx->num_elements <= 8);
/* Note that number of attributes == 0 in the packet means 8
* attributes. This field also contains the offset into shader_rec.
*/
cl_u32(&vc4->bcl, num_elements_emit & 0x7);
/* Note that the primitive type fields match with OpenGL/gallium
* definitions, up to but not including QUADS.
*/
if (info->indexed) {
struct vc4_resource *rsc = vc4_resource(vc4->indexbuf.buffer);
uint32_t offset = vc4->indexbuf.offset;
uint32_t index_size = vc4->indexbuf.index_size;
if (rsc->shadow_parent) {
vc4_update_shadow_index_buffer(pctx, &vc4->indexbuf);
offset = 0;
index_size = 2;
}
cl_start_reloc(&vc4->bcl, 1);
cl_u8(&vc4->bcl, VC4_PACKET_GL_INDEXED_PRIMITIVE);
cl_u8(&vc4->bcl,
info->mode |
(index_size == 2 ?
VC4_INDEX_BUFFER_U16:
VC4_INDEX_BUFFER_U8));
cl_u32(&vc4->bcl, info->count);
cl_reloc(vc4, &vc4->bcl, rsc->bo, offset);
cl_u32(&vc4->bcl, max_index);
} else {
cl_u8(&vc4->bcl, VC4_PACKET_GL_ARRAY_PRIMITIVE);
cl_u8(&vc4->bcl, info->mode);
cl_u32(&vc4->bcl, info->count);
cl_u32(&vc4->bcl, info->start);
}
if (vc4->zsa && vc4->zsa->base.depth.enabled) {
vc4->resolve |= PIPE_CLEAR_DEPTH;
}
if (vc4->zsa && vc4->zsa->base.stencil[0].enabled)
vc4->resolve |= PIPE_CLEAR_STENCIL;
vc4->resolve |= PIPE_CLEAR_COLOR0;
vc4->shader_rec_count++;
if (vc4_debug & VC4_DEBUG_ALWAYS_FLUSH)
vc4_flush(pctx);
}
