static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
struct drm_device *dev = dev_priv->dev;
/*
* After we re-enable the power well, if we touch VGA register 0x3d5
* we'll get unclaimed register interrupts. This stops after we write
* anything to the VGA MSR register. The vgacon module uses this
* register all the time, so if we unbind our driver and, as a
* consequence, bind vgacon, we'll get stuck in an infinite loop at
* console_unlock(). So make here we touch the VGA MSR register, making
* sure vgacon can keep working normally without triggering interrupts
* and error messages.
*/
if (power_well->data == SKL_DISP_PW_2) {
vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
gen8_irq_power_well_post_enable(dev_priv,
1 << PIPE_C | 1 << PIPE_B);
}
if (power_well->data == SKL_DISP_PW_1) {
intel_prepare_ddi(dev);
gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A);
}
}
static void put_status_line( u08 ok __unused, char const * msg )
{
vga_setcolor( 0x0b );
vga_puts( "* " );
vga_setcolor( 0x0f );
vga_puts( msg );
vga_put( '\n' );
}
void panic( char const * file, int line, char const * failure, struct regs * r )
{
vga_puts( "KERNEL PANIC at " );
vga_puts( file );
vga_puts( ":" );
vga_put_dec( line );
vga_puts( "\n\t " );
vga_puts( failure );
vga_puts( "\n" );
if (r)
{ /* dump the reg state: */
put_reg( " ds", r->ds );
put_reg( "edi", r->edi );
put_reg( "esi", r->esi );
put_reg( "ebp", r->ebp );
vga_put( '\n' );
put_reg( "esp", r->esp );
put_reg( "ebx", r->ebx );
put_reg( "edx", r->edx );
put_reg( "ecx", r->ecx );
vga_put( '\n' );
put_reg( "eax", r->eax );
put_reg( "int_no", r->int_no );
put_reg( "err_code", r->err_code );
put_reg( "eip", r->eip );
vga_put( '\n' );
put_reg( "cs", r->cs );
put_reg( "eflags", r->eflags );
put_reg( "user_esp", r->user_esp );
put_reg( "user_ss", r->user_ss );
}
for(;;)
{
disable_interrupts();
halt();
}
}
/*
* Starting with Haswell, we have a "Power Down Well" that can be turned off
* when not needed anymore. We have 4 registers that can request the power well
* to be enabled, and it will only be disabled if none of the registers is
* requesting it to be enabled.
*/
static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
{
struct drm_device *dev = dev_priv->dev;
/*
* After we re-enable the power well, if we touch VGA register 0x3d5
* we'll get unclaimed register interrupts. This stops after we write
* anything to the VGA MSR register. The vgacon module uses this
* register all the time, so if we unbind our driver and, as a
* consequence, bind vgacon, we'll get stuck in an infinite loop at
* console_unlock(). So make here we touch the VGA MSR register, making
* sure vgacon can keep working normally without triggering interrupts
* and error messages.
*/
vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
if (IS_BROADWELL(dev) || (INTEL_INFO(dev)->gen >= 9))
gen8_irq_power_well_post_enable(dev_priv);
}
static void put_reg( char const * name, u32 val )
{
vga_puts( name ); vga_put( '=' );
vga_put_hex( val ); vga_put( ' ' );
}
