/*
* set up everything to get a basic 80x25 textmode.
*/
void
vga_textmode_init(void)
{
vga_sr_write(0x00, 0x01); /* clear reset */
vga_sr_write(0x01, 0x00);
/* set up cr */
vga_cr_mask(0x03, 0x80, 0xE0);
vga_cr_mask(0x05, 0x00, 0x60);
vga_cr_write(0x08, 0x00);
vga_cr_write(0x14, 0x00); /* */
vga_cr_write(0x17, 0x23);
vga_palette_init();
vga_mode_set(640, 648, 680, 776, 792, 800,
400, 407, 412, 414, 442, 449, 320);
vga_cursor_reset();
vga_frame_set(0, 0);
vga_fb_init();
vga_fb_clear();
vga_font_8x16_load();
vga_sr_mask(0x00, 0x02, 0x02); /* take us out of reset */
vga_cr_mask(0x17, 0x80, 0x80); /* sync! */
}
static void
vga_font_8x16_load(void)
{
unsigned char *p;
int i, j;
unsigned char sr2, sr4, gr5, gr6;
#define height 16
#define count 256
sr2 = vga_sr_read(0x02);
sr4 = vga_sr_read(0x04);
gr5 = vga_gr_read(0x05);
gr6 = vga_gr_read(0x06);
/* disable odd/even */
vga_sr_mask(0x04, 0x04, 0x04);
vga_gr_mask(0x05, 0x00, 0x10);
vga_gr_mask(0x06, 0x00, 0x02);
/* plane 2 */
vga_sr_write(0x02, 0x04);
p = (unsigned char *) VGA_FB;
for (i = 0; i < count; i++) {
for (j = 0; j < 32; j++) {
if (j < height)
*p = vga_font_8x16[i][j];
else
*p = 0x00;
p++;
}
}
vga_gr_write(0x06, gr6);
vga_gr_write(0x05, gr5);
vga_sr_write(0x04, sr4);
vga_sr_write(0x02, sr2);
/* set up font size */
vga_cr_mask(0x09, 16 - 1, 0x1F);
}
static void
chrome_vga_init(struct device *dev)
{
vga_sr_write(0x10, 0x01); /* unlock extended regs */
vga_sr_mask(0x1A, 0x02, 0x02); /* enable mmio */
vga_sr_mask(0x1A, 0x40, 0x40); /* Software Reset */
vga_cr_mask(0x6A, 0x00, 0xC8); /* Disable CRTC2 & Simultaneous */
/* Make sure that non of the primary VGA overflow registers are set */
vga_cr_write(0x33, 0x00);
vga_cr_write(0x35, 0x00);
vga_cr_mask(0x11, 0x00, 0x30);
vga_sr_mask(0x16, 0x00, 0x40); /* Wire CRT to CRTC1 */
vga_cr_mask(0x36, 0x00, 0x30); /* Power on CRT */
/* Disable Extended Display Mode */
vga_sr_mask(0x15, 0x00, 0x02);
/* Disable Wrap-around */
vga_sr_mask(0x15, 0x00, 0x20);
/* Disable Extended Mode memory access */
vga_sr_mask(0x1A, 0x00, 0x08);
/* Make sure that we only touch CRTC1s DAC */
vga_sr_mask(0x1A, 0x00, 0x01);
/* Set up power to the clocks/crtcs */
vga_sr_mask(0x19, 0x7F, 0x7F); /* enable clock gating for all. */
vga_sr_mask(0x1B, 0xC0, 0xC0); /* secondary clock according to pm */
vga_sr_mask(0x1B, 0x20, 0x30); /* primary clock is always on */
/* set everything according to PM/Engine idle state except pci dma */
vga_sr_write(0x2D, 0xFF); /* Power management control 1 */
vga_sr_write(0x2E, 0xFB); /* Power management control 2 */
vga_sr_write(0x3F, 0xFF); /* Power management control 3 */
/* now set up the engine clock. */
vga_sr_write(0x47, 0xB8);
vga_sr_write(0x48, 0x08);
vga_sr_write(0x49, 0x03);
/* trigger engine clock setting */
vga_sr_mask(0x40, 0x01, 0x01);
vga_sr_mask(0x40, 0, 0x01);
vga_cr_mask(0x30, 0x04, 0x04); /* Enable PowerNow in primary path */
vga_cr_mask(0x36, 0x01, 0x01); /* Enable PCI Power Management */
/* Power now indicators... */
vga_cr_write(0x41, 0xB9);
vga_cr_write(0x42, 0xB4);
/* could these be the CRTC2 power now indicators? */
vga_cr_write(0x9D, 0x80); /* Power Now Ending position enable */
vga_cr_write(0x9E, 0xB4); /* Power Now Control 3 */
/* primary fifo setting */
vga_sr_mask(0x16, 0x28, 0xBF); /* pthreshold: 160 */
vga_sr_write(0x17, 0x60); /* max depth: 194 */
vga_sr_mask(0x18, 0x0E, 0xBF); /* high priority threshold: 56 */
vga_sr_write(0x1C, 0x54); /* Fetch count */
vga_sr_write(0x20, 0x40); /* display queue typical arbiter control 0 */
vga_sr_write(0x21, 0x40); /* display queue typical arbiter control 1 */
vga_sr_mask(0x22, 0x14, 0x1F); /* display queue expire number */
/* Typical Arbiter Control */
vga_sr_mask(0x41, 0x40, 0xF0); /* Request threshold */
vga_sr_mask(0x42, 0x20, 0x20); /* Support Fetch Cycle with Length 2 */
vga_sr_write(0x50, 0x1F); /* AGP Control Register */
vga_sr_write(0x51, 0xF5); /* AGP FIFO Control 1 */
vga_cr_mask(0x33, 0x08, 0x08); /* Enable Prefetch Mode */
}
