unsigned int
faItrigOutConfig(int id, unsigned short itrigDelay, unsigned short itrigWidth)
{
unsigned int retval=0;
unsigned short s1, s2;
if(id==0) id=fadcID[0];
if((id<=0) || (id>21) || (FAp[id] == NULL)) {
logMsg("faItrigConfig: ERROR : FADC in slot %d is not initialized \n",id,0,0,0,0,0);
return(0xffffffff);
}
if(itrigDelay>FA_ITRIG_MAX_DELAY) itrigDelay = FA_ITRIG_MAX_DELAY;
if(itrigWidth>FA_ITRIG_MAX_WIDTH) itrigWidth = FA_ITRIG_MAX_WIDTH;
FALOCK;
if(itrigWidth)
vmeWrite32(&(FAp[id]->hitsum_trig_width), itrigWidth);
if(itrigDelay)
vmeWrite32(&(FAp[id]->hitsum_trig_delay), itrigDelay);
EIEIO;
s1 = vmeRead32(&(FAp[id]->hitsum_trig_delay))&0xffff;
s2 = vmeRead32(&(FAp[id]->hitsum_trig_width))&0xffff;
retval = (s2<<16)|s1;
FAUNLOCK;
return(retval);
}
void
fadcFirmwareDownloadConfigData(int id)
{
unsigned int ArraySize;
unsigned int ByteCount, ByteIndex, ByteNumber;
unsigned int Word32Bits, SramAdr;
unsigned int value;
if(MSC_loaded != 1)
{
printf("%s: ERROR : Firmware was not loaded\n",
__FUNCTION__);
return;
}
/* ArraySize = sizeof(MSC_ARRAY); */
ArraySize = MSC_arraySize;
ByteIndex = 0;
SramAdr = 0;
/* write SRAM address register */
/* start at 0 and increment address after write to mem1 data register */
FALOCK;
vmeWrite32(&FAp[id]->mem_adr, 0x80000000);
value = vmeRead32(&FAp[id]->mem_adr);
FAUNLOCK;
#ifdef DEBUG
printf("%s: FADC %2d memory address at start of writes = 0x%08x\n\n",
__FUNCTION__,id,value);
#endif
taskDelay(1); /* wait */
/* printf("Download Config Data... \n"); */
for (ByteCount = 0; ByteCount < ArraySize; ByteCount += 4)
{
Word32Bits = 0;
for (ByteNumber = 0; ByteNumber < 4; ++ByteNumber)
{
Word32Bits = (MSC_ARRAY[ByteIndex] << (8 * ByteNumber)) | Word32Bits;
++ByteIndex;
if(ByteIndex>MSC_MAX_SIZE)
printf("**** TOO BIG! ****\n");
}
/* write 32-bit data word to mem1 data register */
FALOCK;
vmeWrite32(&FAp[id]->mem1_data, Word32Bits);
FAUNLOCK;
}
#ifdef DEBUG
FALOCK;
value = vmeRead32(&FAp[id]->mem_adr);
FAUNLOCK;
printf("%s: FADC %2d memory address after write = 0x%08x\n\n",
__FUNCTION__,id,value);
#endif
taskDelay(1); /* wait */
}
void
faItrigPrintHBwidth(int id)
{
int ii;
unsigned int wval[16];
if(id==0) id=fadcID[0];
if((id<=0) || (id>21) || (FAp[id] == NULL)) {
printf("faItrigPrintHBwidth: ERROR : FADC in slot %d is not initialized \n",id);
return;
}
FALOCK;
vmeWrite32(&(FAp[id]->s_adr), FA_SADR_AUTO_INCREMENT);
EIEIO;
for(ii=0;ii<FA_MAX_ADC_CHANNELS;ii++) {
wval[ii] = (vmeRead32(&(FAp[id]->hitsum_hit_width)) + 1)*FA_ADC_NS_PER_CLK; /* Get Values */
}
FAUNLOCK;
printf(" HitBit widths for FADC Inputs in slot %d:",id);
for(ii=0;ii<FA_MAX_ADC_CHANNELS;ii++) {
if((ii%4)==0) printf("\n");
printf("Chan %2d: %3d ns ",(ii+1),wval[ii]);
}
printf("\n");
}
unsigned int
faItrigGetHBwidth(int id, unsigned int chan)
{
unsigned int rval;
if(id==0) id=fadcID[0];
if((id<=0) || (id>21) || (FAp[id] == NULL)) {
logMsg("faItrigGetHBwidth: ERROR : FADC in slot %d is not initialized \n",id,0,0,0,0,0);
return(0xffffffff);
}
if(chan>15) {
logMsg("faItrigGetHBwidth: ERROR : Channel # out of range (0-15)\n",0,0,0,0,0,0);
return(0xffffffff);
}
FALOCK;
vmeWrite32(&(FAp[id]->s_adr), chan); /* Set Channel */
EIEIO;
rval = vmeRead32(&(FAp[id]->hitsum_hit_width)); /* Get Value */
FAUNLOCK;
return(rval);
}
int
faItrigSetHBwidth(int id, unsigned short hbWidth, unsigned short hbMask)
{
int ii;
unsigned int config;
if(id==0) id=fadcID[0];
if((id<=0) || (id>21) || (FAp[id] == NULL)) {
printf("faItrigSetHBwidth: ERROR : FADC in slot %d is not initialized \n",id);
return(ERROR);
}
/* Check and make sure we are not running */
FALOCK;
config = vmeRead32(&(FAp[id]->hitsum_cfg));
if((config&FA_ITRIG_ENABLE_MASK) != FA_ITRIG_DISABLED) {
printf("faItrigSetHBwidth: ERROR: Cannot set HB widths while trigger is Enabled\n");
FAUNLOCK;
return(ERROR);
}
if(hbWidth==0) hbWidth = 1; /* Minimum Width allowed */
if(hbMask==0) hbMask = 0xffff; /* Set all Channels */
for(ii=0;ii<FA_MAX_ADC_CHANNELS;ii++) {
if((1<<ii)&hbMask) {
vmeWrite32(&(FAp[id]->s_adr), ii); /* Set Channel */
vmeWrite32(&(FAp[id]->hitsum_hit_width), hbWidth); /* Set Value */
}
}
FAUNLOCK;
return(OK);
}
/************************************************************
*
* Setup Internal Trigger Table
* 16 input channels can be latched to create a 16 bit
* lookup address (0x0001 - 0xffff) in memory. The value 0 or 1
* at that memory address determines if a trigger pulse will be
* generated (this is for Window or Table mode only)
*
* table = pointer to an array of 65536 values (1 or 0) that
* will define a valid trigger or not.
* (if = NULL, then the default table is loaded - all
* input combinations will generate a trigger)
*/
int
faItrigInitTable(int id, unsigned int *table)
{
int ii;
unsigned int config;
if(id==0) id=fadcID[0];
if((id<=0) || (id>21) || (FAp[id] == NULL)) {
printf("faItrigSetMode: ERROR : FADC in slot %d is not initialized \n",id);
return(ERROR);
}
FALOCK;
/* Check and make sure we are not running */
config = vmeRead32(&(FAp[id]->hitsum_cfg));
if((config&FA_ITRIG_ENABLE_MASK) != FA_ITRIG_DISABLED) {
printf("faItrigInitTable: ERROR: Cannot update Trigger Table while trigger is Enabled\n");
FAUNLOCK;
return(ERROR);
}
if(table == NULL) {
/* Use default Initialization - all combinations of inputs will be a valid trigger */
vmeWrite32(&(FAp[id]->s_adr), FA_SADR_AUTO_INCREMENT);
vmeWrite32(&(FAp[id]->hitsum_pattern), 0); /* Make sure address 0 is not a valid trigger */
for(ii=1;ii<=0xffff;ii++) {
vmeWrite32(&(FAp[id]->hitsum_pattern), 1);
}
}else{ /* Load specified table into hitsum FPGA */
vmeWrite32(&(FAp[id]->s_adr), FA_SADR_AUTO_INCREMENT);
vmeWrite32(&(FAp[id]->hitsum_pattern), 0); /* Make sure address 0 is not a valid trigger */
for(ii=1;ii<=0xffff;ii++) {
if(table[ii])
vmeWrite32(&(FAp[id]->hitsum_pattern), 1);
else
vmeWrite32(&(FAp[id]->hitsum_pattern), 0);
}
}
FAUNLOCK;
return(OK);
}
void
faItrigDisable(int id)
{
unsigned int rval;
if(id==0) id=fadcID[0];
if((id<=0) || (id>21) || (FAp[id] == NULL)) {
logMsg("faItrigDisable: ERROR : FADC in slot %d is not initialized \n",id,0,0,0,0,0);
return;
}
FALOCK;
rval = vmeRead32(&(FAp[id]->hitsum_cfg));
rval |= FA_ITRIG_DISABLED;
vmeWrite32(&(FAp[id]->hitsum_cfg), rval);
FAUNLOCK;
}
int
faItrigGetTableVal (int id, unsigned short pMask)
{
unsigned int rval;
if(id==0) id=fadcID[0];
if((id<=0) || (id>21) || (FAp[id] == NULL)) {
logMsg("faItrigTableStatus: ERROR : FADC in slot %d is not initialized \n",id,0,0,0,0,0);
return(ERROR);
}
FALOCK;
vmeWrite32(&(FAp[id]->s_adr), pMask);
EIEIO; /* Make sure write comes before read */
rval = vmeRead32(&(FAp[id]->hitsum_pattern));
FAUNLOCK;
if(rval)
return(1);
else
return(0);
}
int
fadcFirmwareZeroSRAM (int id)
{
int ii, value=0, value_1=0, value_2=0;
int ErrorCount=0, stopPrint=0;
if(id==0) id=fadcID[0];
if((id<=0) || (id>21) || (FAp[id] == NULL))
{
printf("%s: ERROR : ADC in slot %d is not initialized \n",
__FUNCTION__,id);
return ERROR;
}
/* set address = 0; allow increment on mem2 access */
FALOCK;
vmeWrite32(&FAp[id]->mem_adr, 0x0000 | FA_MEM_ADR_INCR_MEM2);
for( ii = 0; ii < 0x80000; ii++) /* write ZERO to entire memory */
{
vmeWrite32(&FAp[id]->mem1_data, 0);
vmeWrite32(&FAp[id]->mem2_data, 0);
}
/* reset address = 0; allow increment on mem2 access */
vmeWrite32(&FAp[id]->mem_adr, 0x0000 | FA_MEM_ADR_INCR_MEM2);
FAUNLOCK;
/* read and test expected memory data */
for( ii = 0; ii < 0x80000; ii++)
{
FALOCK;
value_1 = vmeRead32(&FAp[id]->mem1_data);
value_2 = vmeRead32(&FAp[id]->mem2_data);
FAUNLOCK;
if( (value_1 != 0) || (value_2 != 0) )
{
ErrorCount++;
FALOCK;
value = vmeRead32(&FAp[id]->mem_adr) & 0xFFFFF;
FAUNLOCK;
if(!stopPrint)
{
printf("%s: ERROR: FADC %2d address = %8X mem1 read = %8X mem2 read = %8X\n",
__FUNCTION__,id,
value, value_1, value_2);
taskDelay(1); /* wait */
}
if(ErrorCount==80)
{
printf("%s: Further errors for FADC %2d will not be displayed\n",
__FUNCTION__,id);
stopPrint=1;
}
}
}
if(ErrorCount)
return ERROR;
return OK;
}
int
fadcFirmwareVerifyDownload (int id)
{
unsigned int ArraySize;
unsigned int ByteCount, ByteIndex, ByteNumber;
unsigned int ExpWord32Bits, SramAdr, RdWord32Bits;
int ErrorCount=0, stopPrint=0;
int value;
if(id==0) id=fadcID[0];
if((id<=0) || (id>21) || (FAp[id] == NULL))
{
printf("%s: ERROR : ADC in slot %d is not initialized \n",
__FUNCTION__,id);
return ERROR;
}
if(MSC_loaded != 1)
{
printf("%s: ERROR : Firmware was not loaded\n",
__FUNCTION__);
return ERROR;
}
/* ArraySize = sizeof(MSC_ARRAY); */
ArraySize = MSC_arraySize;
ByteIndex = 0;
SramAdr = 0;
/* write SRAM address register */
/* start at 0 and increment address after read from mem1 data register */
FALOCK;
vmeWrite32(&FAp[id]->mem_adr, 0x0000 | FA_MEM_ADR_INCR_MEM1);
value = vmeRead32(&FAp[id]->mem_adr);
FAUNLOCK;
#ifdef DEBUG
printf("%s: FADC %2d memory address at start of read = 0x%08x\n\n",
__FUNCTION__,id,value);
#endif
taskDelay(2); /* wait */
for (ByteCount = 0; ByteCount < ArraySize; ByteCount += 4)
{
/* get expected value */
ExpWord32Bits = 0;
for (ByteNumber = 0; ByteNumber < 4; ++ByteNumber)
{
ExpWord32Bits = (MSC_ARRAY[ByteIndex] << (8 * ByteNumber)) | ExpWord32Bits;
++ByteIndex;
}
/* read 32-bit data word from mem1 data register */
FALOCK;
RdWord32Bits = (unsigned int)vmeRead32(&FAp[id]->mem1_data);
FAUNLOCK;
#ifdef DEBUG
if(ByteCount<40)
printf("RdWord32Bits = 0x%08x\n",RdWord32Bits);
#endif
/* test if read value = expected value */
if (RdWord32Bits != ExpWord32Bits)
{
ErrorCount++;
if(!stopPrint)
printf("%s: ERROR: FADC %2d ByteCount %8d Expect %08X Read %08X\n",
__FUNCTION__,id,
ByteCount, ExpWord32Bits, RdWord32Bits);
if( ErrorCount==80 )
{
printf("%s: Further errors for FADC %2d will not be displayed\n",
__FUNCTION__,id);
/* getchar(); */
stopPrint=1;
}
/* if( ErrorCount>1000 ) */
/* stopPrint=1; */
}
}
FALOCK;
value = vmeRead32(&FAp[id]->mem_adr);
FAUNLOCK;
#ifdef DEBUG
printf("%s: memory address after read = 0x%08x\n\n",
__FUNCTION__,value);
#endif
if(ErrorCount)
printf("%s: ErrorCount = %d\n",__FUNCTION__,ErrorCount);
taskDelay(1); /* wait */
if(ErrorCount)
return ERROR;
return OK;
}
int
fadcFirmwareLoad(int id, int chip, int pFlag)
{
if(id==0) id=fadcID[0];
if((id<=0) || (id>21) || (FAp[id] == NULL))
{
printf("%s: ERROR : ADC in slot %d is not initialized \n",
__FUNCTION__,id);
return ERROR;
}
if(chip<0 || chip>2)
{
printf("%s: ERROR: Invalid chip parameter %d\n",
__FUNCTION__,chip);
return ERROR;
}
/* Perform a hardware and software reset */
FALOCK;
vmeWrite32(&FAp[id]->reset, 0xFFFF);
FAUNLOCK;
taskDelay(60);
/* Check if FADC is Ready */
if(fadcFirmwareTestReady(id, 60, pFlag) != OK)
{
printf("%s: ERROR: FADC %2d not ready after reset\n",
__FUNCTION__,id);
return ERROR;
}
/* Data to SRAM */
printf("%s: Loading SRAM with data \n",__FUNCTION__);
fadcFirmwareDownloadConfigData(id);
if(fadcFirmwareVerifyDownload(id) != OK)
{
printf("%s: ERROR: FADC %2d Failed data verification at SRAM\n",
__FUNCTION__,id);
return ERROR;
}
/* SRAM TO PROM */
taskDelay(1);
printf("%s: Loading PROM with SRAM data \n",__FUNCTION__);
FALOCK;
if(chip==FADC_FIRMWARE_LX110)
vmeWrite32(&FAp[id]->prom_reg1,FA_PROMREG1_SRAM_TO_PROM1);
else if(chip==FADC_FIRMWARE_FX70T)
vmeWrite32(&FAp[id]->prom_reg1,FA_PROMREG1_SRAM_TO_PROM2);
FAUNLOCK;
taskDelay(1);
if(fadcFirmwareTestReady(id, 60000, pFlag) != OK) /* Wait til it's done */
{
printf("%s: ERROR: FADC %2d ready timeout SRAM -> PROM\n",
__FUNCTION__,id);
return ERROR;
}
/* PROM TO SRAM (For verification) */
printf("%s: Loading SRAM with PROM data \n",__FUNCTION__);
fadcFirmwareZeroSRAM(id);
FALOCK;
if(chip==FADC_FIRMWARE_LX110)
vmeWrite32(&FAp[id]->prom_reg1,FA_PROMREG1_PROM1_TO_SRAM);
else if(chip==FADC_FIRMWARE_FX70T)
vmeWrite32(&FAp[id]->prom_reg1,FA_PROMREG1_PROM2_TO_SRAM);
FAUNLOCK;
taskDelay(1);
if(fadcFirmwareTestReady(id, 60000, pFlag) != OK) /* Wait til it's done */
{
printf("%s: ERROR: FADC %2d ready timeout PROM -> SRAM\n",
__FUNCTION__,id);
return ERROR;
}
/* Compare SRAM to Data Array */
printf("%s: Verifying data \n",__FUNCTION__);
if(fadcFirmwareVerifyDownload(id) != OK)
{
printf("%s: ERROR: FADC %d PROM data not verified\n",
__FUNCTION__,id);
return ERROR;
}
/* PROM to FPGA (Reboot FPGA) */
printf("%s: Rebooting FPGA \n",__FUNCTION__);
FALOCK;
if(chip==FADC_FIRMWARE_LX110)
vmeWrite32(&FAp[id]->prom_reg1,FA_PROMREG1_REBOOT_FPGA1);
else if(chip==FADC_FIRMWARE_FX70T)
vmeWrite32(&FAp[id]->prom_reg1,FA_PROMREG1_REBOOT_FPGA2);
FAUNLOCK;
taskDelay(1);
if(fadcFirmwareTestReady(id, 60000, pFlag) != OK) /* Wait til it's done */
{
printf("%s: ERROR: FADC %2d ready timeout PROM -> FPGA\n",
__FUNCTION__,id);
return ERROR;
}
printf("%s: Done programming FADC %2d\n",
__FUNCTION__,id);
return OK;
}
/*************************************************************
* fadcFirmwareGLoad
* - load up firmware for all initialized modules
*
* NOTE: Make call to
* fadcFirmwareSetFilename(...);
* if not using firmware from the default
*/
int
fadcFirmwareGLoad(int chip, int pFlag)
{
int ifadc=0, id=0, step=0;
unsigned int passed[FA_MAX_BOARDS+1], stepfail[FA_MAX_BOARDS+1];
if(chip<0 || chip>2)
{
printf("%s: ERROR: Invalid chip parameter %d\n",
__FUNCTION__,chip);
return ERROR;
}
/* Perform a hardware and software reset */
step=0;
FALOCK;
for(ifadc=0 ; ifadc<nfadc; ifadc++)
{
id = fadcID[ifadc];
if((id<=0) || (id>21) || (FAp[id] == NULL))
{
printf("%s: ERROR : ADC in slot %d is not initialized \n",
__FUNCTION__,id);
passed[id] = 0;
stepfail[id] = step;
}
else
{
passed[id] = 1;
vmeWrite32(&FAp[id]->reset, 0xFFFF);
}
}
FAUNLOCK;
taskDelay(60);
/* Check if FADC is Ready */
step=1;
for(ifadc=0 ; ifadc<nfadc; ifadc++)
{
id = fadcID[ifadc];
if(fadcFirmwareTestReady(id, 60, pFlag) != OK)
{
printf("%s: ERROR: FADC %2d not ready after reset\n",
__FUNCTION__,id);
passed[id] = 0;
stepfail[id] = step;
}
}
/* Data to SRAM */
step=2;
printf("%s: Loading SRAM with data \n",__FUNCTION__);
for(ifadc=0 ; ifadc<nfadc; ifadc++)
{
id = fadcID[ifadc];
printf("%2d: ",id);
fflush(stdout);
if(passed[id]) /* Skip the ones that have previously failed */
{
fadcFirmwareDownloadConfigData(id);
if(fadcFirmwareVerifyDownload(id) != OK)
{
printf("%s: ERROR: FADC %2d Failed data verification at SRAM\n",
__FUNCTION__,id);
passed[id] = 0;
stepfail[id] = step;
}
else
printf(" Done\n");
}
}
/* SRAM TO PROM */
step=3;
taskDelay(1);
printf("%s: Loading PROM with SRAM data \n",__FUNCTION__);
FALOCK;
for(ifadc=0 ; ifadc<nfadc; ifadc++)
{
id = fadcID[ifadc];
if(passed[id]) /* Skip the ones that have previously failed */
{
if(chip==FADC_FIRMWARE_LX110)
vmeWrite32(&FAp[id]->prom_reg1,FA_PROMREG1_SRAM_TO_PROM1);
else if(chip==FADC_FIRMWARE_FX70T)
vmeWrite32(&FAp[id]->prom_reg1,FA_PROMREG1_SRAM_TO_PROM2);
}
}
FAUNLOCK;
taskDelay(1);
for(ifadc=0 ; ifadc<nfadc; ifadc++)
{
id = fadcID[ifadc];
if(passed[id]) /* Skip the ones that have previously failed */
{
if(fadcFirmwareTestReady(id, 60000, pFlag) != OK) /* Wait til it's done */
{
printf("%s: ERROR: FADC %2d ready timeout SRAM -> PROM\n",
__FUNCTION__,id);
passed[id] = 0;
stepfail[id] = step;
}
}
}
/* PROM TO SRAM (For verification) */
printf("%s: Loading SRAM with PROM data \n",__FUNCTION__);
step=4;
for(ifadc=0 ; ifadc<nfadc; ifadc++)
{
id = fadcID[ifadc];
if(passed[id]) /* Skip the ones that have previously failed */
{
fadcFirmwareZeroSRAM(id);
FALOCK;
if(chip==FADC_FIRMWARE_LX110)
vmeWrite32(&FAp[id]->prom_reg1,FA_PROMREG1_PROM1_TO_SRAM);
else if(chip==FADC_FIRMWARE_FX70T)
vmeWrite32(&FAp[id]->prom_reg1,FA_PROMREG1_PROM2_TO_SRAM);
FAUNLOCK;
}
}
taskDelay(1);
for(ifadc=0 ; ifadc<nfadc; ifadc++)
{
id = fadcID[ifadc];
if(passed[id]) /* Skip the ones that have previously failed */
{
if(fadcFirmwareTestReady(id, 60000, pFlag) != OK) /* Wait til it's done */
{
printf("%s: ERROR: FADC %2d ready timeout PROM -> SRAM\n",
__FUNCTION__,id);
passed[id] = 0;
stepfail[id] = step;
}
}
}
/* Compare SRAM to Data Array */
printf("%s: Verifying data \n",__FUNCTION__);
step=5;
for(ifadc=0 ; ifadc<nfadc; ifadc++)
{
id = fadcID[ifadc];
printf("%2d: ",id);
fflush(stdout);
if(passed[id]) /* Skip the ones that have previously failed */
{
if(fadcFirmwareVerifyDownload(id) != OK)
{
printf("%s: ERROR: FADC %d PROM data not verified\n",
__FUNCTION__,id);
passed[id] = 0;
stepfail[id] = step;
}
else
printf(" Done\n");
}
}
/* PROM to FPGA (Reboot FPGA) */
printf("%s: Rebooting FPGA \n",__FUNCTION__);
step=6;
for(ifadc=0 ; ifadc<nfadc; ifadc++)
{
id = fadcID[ifadc];
if(passed[id]) /* Skip the ones that have previously failed */
{
FALOCK;
if(chip==FADC_FIRMWARE_LX110)
vmeWrite32(&FAp[id]->prom_reg1,FA_PROMREG1_REBOOT_FPGA1);
else if(chip==FADC_FIRMWARE_FX70T)
vmeWrite32(&FAp[id]->prom_reg1,FA_PROMREG1_REBOOT_FPGA2);
FAUNLOCK;
}
}
taskDelay(1);
for(ifadc=0 ; ifadc<nfadc; ifadc++)
{
id = fadcID[ifadc];
if(passed[id]) /* Skip the ones that have previously failed */
{
if(fadcFirmwareTestReady(id, 60000, pFlag) != OK) /* Wait til it's done */
{
printf("%s: ERROR: FADC %2d ready timeout PROM -> FPGA\n",
__FUNCTION__,id);
passed[id] = 0;
stepfail[id] = step;
}
}
}
for(ifadc=0 ; ifadc<nfadc; ifadc++)
{
id = fadcID[ifadc];
if(passed[id]) /* Skip the ones that have previously failed */
{
printf("%s: Done programming FADC %2d\n",
__FUNCTION__,id);
}
else
{
printf("%s: FAILED programming FADC %2d at step %d\n",
__FUNCTION__,id,stepfail[id]);
}
}
return OK;
}
/************************************************************
*
* Setup Internal Triggering
*
* Four Modes of Operation (tmode)
* 1) Table Mode
* 2) Window Mode
* 3) Coincidence Mode
* 4) Sum Mode
*
* wMask = Mask of 16 channels to be enabled for Window Mode
* wWidth = Width of trigger window before latching (in clocks)
* cMask = Mask of 16 channels to be enabled for Coincidence Mode
* sumThresh = 10-12 bit threshold for Sum trigger to be latched
* tTable = pointer to trigger table (65536 values) to be loaded
*/
int
faItrigSetMode(int id, int tmode, unsigned int wMask, unsigned int wWidth,
unsigned int cMask, unsigned int sumThresh, unsigned int *tTable)
{
int ii;
unsigned int config, stat, wTime;
if(id==0) id=fadcID[0];
if((id<=0) || (id>21) || (FAp[id] == NULL)) {
printf("faItrigSetMode: ERROR : FADC in slot %d is not initialized \n",id);
return(ERROR);
}
/* Make sure we are not enabled or running */
FALOCK;
config = vmeRead32(&(FAp[id]->hitsum_cfg))&FA_ITRIG_CONFIG_MASK;
if((config&FA_ITRIG_ENABLE_MASK) == 0) {
printf("faItrigSetMode: ERROR: Internal triggers are enabled - Disable first\n");
FAUNLOCK;
return(ERROR);
}
if((tmode<1)||(tmode>4)) {
printf("faItrigSetMode: ERROR: Trigger mode (%d) out of range (tmode = 1-4)\n",tmode);
FAUNLOCK;
return(ERROR);
}
/* Check if we need to load a trigger table */
if(tTable != NULL) {
printf("faItrigSetMode: Loading trigger table from address 0x%08x \n",(unsigned int) tTable);
vmeWrite32(&(FAp[id]->s_adr), FA_SADR_AUTO_INCREMENT);
vmeWrite32(&(FAp[id]->hitsum_pattern), 0); /* Make sure address 0 is not a valid trigger */
for(ii=1;ii<=0xffff;ii++) {
if(tTable[ii])
vmeWrite32(&(FAp[id]->hitsum_pattern), 1);
else
vmeWrite32(&(FAp[id]->hitsum_pattern), 0);
}
}
switch(tmode) {
case FA_ITRIG_SUM_MODE:
/* Load Sum Threshhold if in range */
if((sumThresh > 0)&&(sumThresh <= 0xffff)) {
vmeWrite32(&(FAp[id]->hitsum_sum_thresh), sumThresh);
}else{
printf("faItrigSetMode: ERROR: Sum Threshold out of range (0<st<=0xffff)\n");
FAUNLOCK;
return(ERROR);
}
stat = (config&~FA_ITRIG_MODE_MASK) | FA_ITRIG_SUM_MODE;
vmeWrite32(&(FAp[id]->hitsum_cfg), stat);
printf("faItrigSetMode: Configure for SUM Mode (Threshold = 0x%x)\n",sumThresh);
break;
case FA_ITRIG_COIN_MODE:
/* Set Coincidence Input Channels */
if((cMask > 0)&&(cMask <= 0xffff)) {
vmeWrite32(&(FAp[id]->hitsum_coin_bits), cMask);
}else{
printf("faItrigSetMode: ERROR: Coincidence channel mask out of range (0<cc<=0xffff)\n");
FAUNLOCK;
return(ERROR);
}
stat = (config&~FA_ITRIG_MODE_MASK) | FA_ITRIG_COIN_MODE;
vmeWrite32(&(FAp[id]->hitsum_cfg), stat);
printf("faItrigSetMode: Configure for COINCIDENCE Mode (channel mask = 0x%x)\n",cMask);
break;
case FA_ITRIG_WINDOW_MODE:
/* Set Trigger Window width and channel mask */
if((wMask > 0)&&(wMask <= 0xffff)) {
vmeWrite32(&(FAp[id]->hitsum_window_bits), wMask);
}else{
printf("faItrigSetMode: ERROR: Trigger Window channel mask out of range (0<wc<=0xffff)\n");
FAUNLOCK;
return(ERROR);
}
if((wWidth > 0)&&(wWidth <= FA_ITRIG_WINDOW_MAX_WIDTH)) {
vmeWrite32(&(FAp[id]->hitsum_window_width), wWidth);
wTime = 4*wWidth;
}else{
printf("faItrigSetMode: ERROR: Trigger Window width out of range (0<ww<=0x200)\n");
FAUNLOCK;
return(ERROR);
}
stat = (config&~FA_ITRIG_MODE_MASK) | FA_ITRIG_WINDOW_MODE;
vmeWrite32(&(FAp[id]->hitsum_cfg), stat);
printf("faItrigSetMode: Configure for Trigger WINDOW Mode (channel mask = 0x%x, width = %d ns)\n",
cMask,wTime);
break;
case FA_ITRIG_TABLE_MODE:
stat = (config&~FA_ITRIG_MODE_MASK) | FA_ITRIG_TABLE_MODE;
vmeWrite32(&(FAp[id]->hitsum_cfg), stat);
printf("faItrigSetMode: Configure for Trigger TABLE Mode\n");
}
FAUNLOCK;
return(OK);
}
