static int vpe_reset(void)
{
uint32_t vpe_version;
uint32_t rc = 0;
/* */
unsigned long flags = 0;
spin_lock_irqsave(&vpe_ctrl->lock, flags);
if (vpe_ctrl->state == VPE_STATE_IDLE) {
CDBG("%s: VPE already disabled.", __func__);
spin_unlock_irqrestore(&vpe_ctrl->lock, flags);
return rc;
}
spin_unlock_irqrestore(&vpe_ctrl->lock, flags);
/* */
vpe_reset_state_variables();
vpe_version = msm_io_r(vpe_ctrl->vpebase + VPE_HW_VERSION_OFFSET);
CDBG("vpe_version = 0x%x\n", vpe_version);
/* disable all interrupts.*/
msm_io_w(0, vpe_ctrl->vpebase + VPE_INTR_ENABLE_OFFSET);
/* clear all pending interrupts*/
msm_io_w(0x1fffff, vpe_ctrl->vpebase + VPE_INTR_CLEAR_OFFSET);
/* write sw_reset to reset the core. */
msm_io_w(0x10, vpe_ctrl->vpebase + VPE_SW_RESET_OFFSET);
/* then poll the reset bit, it should be self-cleared. */
while (1) {
rc =
msm_io_r(vpe_ctrl->vpebase + VPE_SW_RESET_OFFSET) & 0x10;
if (rc == 0)
break;
}
/* at this point, hardware is reset. Then pogram to default
values. */
msm_io_w(VPE_AXI_RD_ARB_CONFIG_VALUE,
vpe_ctrl->vpebase + VPE_AXI_RD_ARB_CONFIG_OFFSET);
msm_io_w(VPE_CGC_ENABLE_VALUE,
vpe_ctrl->vpebase + VPE_CGC_EN_OFFSET);
msm_io_w(1, vpe_ctrl->vpebase + VPE_CMD_MODE_OFFSET);
msm_io_w(VPE_DEFAULT_OP_MODE_VALUE,
vpe_ctrl->vpebase + VPE_OP_MODE_OFFSET);
msm_io_w(VPE_DEFAULT_SCALE_CONFIG,
vpe_ctrl->vpebase + VPE_SCALE_CONFIG_OFFSET);
vpe_config_axi_default();
return rc;
}
static int vpe_reset(void)
{
uint32_t vpe_version;
uint32_t rc;
vpe_reset_state_variables();
vpe_version = msm_camera_io_r(
vpe_device->vpebase + VPE_HW_VERSION_OFFSET);
CDBG("vpe_version = 0x%x\n", vpe_version);
/* disable all interrupts.*/
msm_camera_io_w(0, vpe_device->vpebase + VPE_INTR_ENABLE_OFFSET);
/* clear all pending interrupts*/
msm_camera_io_w(0x1fffff, vpe_device->vpebase + VPE_INTR_CLEAR_OFFSET);
/* write sw_reset to reset the core. */
msm_camera_io_w(0x10, vpe_device->vpebase + VPE_SW_RESET_OFFSET);
/* then poll the reset bit, it should be self-cleared. */
while (1) {
rc = msm_camera_io_r(vpe_device->vpebase + VPE_SW_RESET_OFFSET)
& 0x10;
if (rc == 0)
break;
}
/* at this point, hardware is reset. Then pogram to default
values. */
msm_camera_io_w(VPE_AXI_RD_ARB_CONFIG_VALUE,
vpe_device->vpebase + VPE_AXI_RD_ARB_CONFIG_OFFSET);
msm_camera_io_w(VPE_CGC_ENABLE_VALUE,
vpe_device->vpebase + VPE_CGC_EN_OFFSET);
msm_camera_io_w(1, vpe_device->vpebase + VPE_CMD_MODE_OFFSET);
msm_camera_io_w(VPE_DEFAULT_OP_MODE_VALUE,
vpe_device->vpebase + VPE_OP_MODE_OFFSET);
msm_camera_io_w(VPE_DEFAULT_SCALE_CONFIG,
vpe_device->vpebase + VPE_SCALE_CONFIG_OFFSET);
vpe_config_axi_default();
return 0;
}
static int vpe_reset(void)
{
uint32_t vpe_version;
uint32_t rc = 0;
unsigned long flags = 0;
spin_lock_irqsave(&vpe_ctrl->lock, flags);
if (vpe_ctrl->state == VPE_STATE_IDLE) {
pr_info("%s: VPE already disabled.", __func__);
spin_unlock_irqrestore(&vpe_ctrl->lock, flags);
return rc;
}
spin_unlock_irqrestore(&vpe_ctrl->lock, flags);
pr_info("%s, vpe_ctrl->state %d\n", __func__, vpe_ctrl->state);
vpe_reset_state_variables();
vpe_version = msm_io_r(vpe_ctrl->vpebase + VPE_HW_VERSION_OFFSET);
CDBG("vpe_version = 0x%x\n", vpe_version);
msm_io_w(0, vpe_ctrl->vpebase + VPE_INTR_ENABLE_OFFSET);
msm_io_w(0x1fffff, vpe_ctrl->vpebase + VPE_INTR_CLEAR_OFFSET);
msm_io_w(0x10, vpe_ctrl->vpebase + VPE_SW_RESET_OFFSET);
while (1) {
rc =
msm_io_r(vpe_ctrl->vpebase + VPE_SW_RESET_OFFSET) & 0x10;
if (rc == 0)
break;
}
msm_io_w(VPE_AXI_RD_ARB_CONFIG_VALUE,
vpe_ctrl->vpebase + VPE_AXI_RD_ARB_CONFIG_OFFSET);
msm_io_w(VPE_CGC_ENABLE_VALUE,
vpe_ctrl->vpebase + VPE_CGC_EN_OFFSET);
msm_io_w(1, vpe_ctrl->vpebase + VPE_CMD_MODE_OFFSET);
msm_io_w(VPE_DEFAULT_OP_MODE_VALUE,
vpe_ctrl->vpebase + VPE_OP_MODE_OFFSET);
msm_io_w(VPE_DEFAULT_SCALE_CONFIG,
vpe_ctrl->vpebase + VPE_SCALE_CONFIG_OFFSET);
vpe_config_axi_default();
return rc;
}
