static int ahci_phy_init(void __iomem *mmio)
{
int i, ctrl0;
for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_cmu); i++)
__raw_writeb(exynos4_sataphy_cmu[i].val,
phy_base + (exynos4_sataphy_cmu[i].reg * 4));
for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_lane); i++)
__raw_writeb(exynos4_sataphy_lane[i].val,
phy_base + (LANE0 + exynos4_sataphy_lane[i].reg) * 4);
for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_comlane); i++)
__raw_writeb(exynos4_sataphy_comlane[i].val,
phy_base + (COM_LANE + exynos4_sataphy_comlane[i].reg) * 4);
__raw_writeb(0x07, phy_base);
ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
ctrl0 |= SATA_CTRL0_PHY_CMU_RST_N;
__raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS,
SATA_PHY_STATUS_CMU_OK) < 0) {
printk(KERN_ERR "PHY CMU not ready\n");
return -EBUSY;
}
__raw_writeb(0x03, phy_base + (COM_LANE * 4));
ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
ctrl0 |= SATA_CTRL0_M_PHY_LN_RST_N;
__raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS,
SATA_PHY_STATUS_LANE_OK) < 0) {
printk(KERN_ERR "PHY LANE not ready\n");
return -EBUSY;
}
ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
ctrl0 |= SATA_CTRL0_M_PHY_CAL;
__raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
return 0;
}
static int mrvl_usb_phy_28nm_init(u32 base)
{
struct usb_file *file = (struct usb_file *)(uintptr_t)base;
u32 tmp32;
int ret;
/*
* pll control 0:
* 0xd420_7000[6:0] = 0xd, b'000_1101 ---> REFDIV
* 0xd420_7000[24:16] = 0xf0, b'1111_0000 ---> FBDIV
* 0xd420_7000[11:8] = 0x3, b'0011 ---> ICP
* 0xd420_7000[29:28] = 0x1, b'01 ---> SEL_LPFR
*/
tmp32 = readl(&file->pll_reg0);
tmp32 &= ~(REFDIV_MASK | FB_DIV_MASK | ICP_MASK | SEL_LPFR_MASK);
tmp32 |= REFDIV(0xd) | FB_DIV(0xf0) | ICP(0x3) | SEL_LPFR(0x1);
writel(tmp32, &file->pll_reg0); /*
* pll control 1:
* 0xd420_7004[1:0] = 0x3, b'11 ---> [PU_PLL_BY_REG:PU_PLL]
*/
tmp32 = readl(&file->pll_reg1);
tmp32 &= ~(PLL_PU_MASK | PU_BY_MASK);
tmp32 |= PLL_PU(0x1) | PU_BY(0x1);
writel(tmp32, &file->pll_reg1);
/*
* tx reg 0:
* 0xd420_700c[22:20] = 0x3, b'11 ---> AMP
*/
tmp32 = readl(&file->tx_reg0);
tmp32 &= ~(AMP_MASK);
tmp32 |= AMP(0x3);
writel(tmp32, &file->tx_reg0);
/*
* rx reg 0:
* 0xd420_7018[3:0] = 0xa, b'1010 ---> SQ_THRESH
*/
tmp32 = readl(&file->rx_reg0);
tmp32 &= ~(SQ_THRESH_MASK);
tmp32 |= SQ_THRESH(0xa);
writel(tmp32, &file->rx_reg0);
/*
* dig reg 0:
* 0xd420_701c[31] = 0, b'0 ---> BITSTAFFING_ERROR
* 0xd420_701c[30] = 0, b'0 ---> LOSS_OF_SYNC_ERROR
* 0xd420_701c[18:16] = 0x7, b'111 ---> SQ_FILT
* 0xd420_701c[14:12] = 0x4, b'100 ---> SQ_BLK
* 0xd420_701c[1:0] = 0x2, b'10 ---> SYNC_NUM
*/
tmp32 = readl(&file->dig_reg0);
tmp32 &= ~(BITSTAFFING_ERR_MASK | SYNC_ERR_MASK | SQ_FILT_MASK | SQ_BLK_MASK | SYNC_NUM_MASK);
tmp32 |= (SQ_FILT(0x0) | SQ_BLK(0x0) | SYNC_NUM(0x1));
writel(tmp32, &file->dig_reg0);
/*
* otg reg:
* 0xd420_7034[5:4] = 0x1, b'01 ---> [OTG_CONTROL_BY_PIN:PU_OTG]
*/
tmp32 = readl(&file->otg_reg);
tmp32 &= ~(OTG_CTRL_BY_MASK | PU_OTG_MASK);
tmp32 |= OTG_CTRL_BY(0x0) | PU_OTG(0x1);
writel(tmp32, &file->otg_reg);
/*
* tx reg 0:
* 0xd420_700c[25:24] = 0x3, b'11 ---> [PU_ANA:PU_BY_REG]
*/
tmp32 = readl(&file->tx_reg0);
tmp32 &= ~(ANA_PU_MASK | TX_PU_BY_MASK);
tmp32 |= ANA_PU(0x1) | TX_PU_BY(0x1);
writel(tmp32, &file->tx_reg0);
udelay(400);
ret = wait_for_phy_ready(file);
if (ret < 0) {
printf("initialize usb phy failed, dump usb registers:\n");
dump_phy_regs(base);
}
printf("usb phy inited 0x%x!\n", readl(&file->usb_ctrl0));
return 0;
}
