void PLL1Init()
{
//594 version
//Uint32 PLL1_Mult = 22;
//567 version - use with 189 MHZ DDR
//Uint32 PLL1_Mult = 21;
// Set PLL2 clock input to internal osc.
PLL1->PLLCTL &= (~0x00000100);
// Clear PLLENSRC bit and clear PLLEN bit for Bypass mode
PLL1->PLLCTL &= (~0x00000021);
// Wait for PLLEN mux to switch
waitloop(32);
PLL1->PLLCTL &= (~0x00000008); // Put PLL into reset
PLL1->PLLCTL |= (0x00000010); // Disable the PLL
PLL1->PLLCTL &= (~0x00000002); // Power-up the PLL
PLL1->PLLCTL &= (~0x00000010); // Enable the PLL
// Set PLL multipliers and divisors
PLL1->PLLM = PLL1_Mult - 1; // 27Mhz * (21+1) = 594 MHz
PLL1->PLLCMD |= 0x00000001; // Tell PLL to do phase alignment
while ((PLL1->PLLSTAT) & 0x1); // Wait until done
waitloop(256);
PLL1->PLLCTL |= (0x00000008); // Take PLL out of reset
waitloop(2000); // Wait for locking
PLL1->PLLCTL |= (0x00000001); // Switch out of bypass mode
}
void PLL2Init()
{
// Set PLL2 clock input to external osc.
PLL2->PLLCTL &= (~0x00000100);
// Clear PLLENSRC bit and clear PLLEN bit for Bypass mode
PLL2->PLLCTL &= (~0x00000021);
// Wait for PLLEN mux to switch
waitloop(32*(PLL1_Mult/2));
PLL2->PLLCTL &= (~0x00000008); // Put PLL into reset
PLL2->PLLCTL |= (0x00000010); // Disable the PLL
PLL2->PLLCTL &= (~0x00000002); // Power-up the PLL
PLL2->PLLCTL &= (~0x00000010); // Enable the PLL
// Set PLL multipliers and divisors
PLL2->PLLM = PLL2_Mult-1; // 27 Mhz * (23+1) = 648 MHz
PLL2->PLLDIV1 = PLL2_Div1-1; // 648 MHz / (11+1) = 54 MHz
PLL2->PLLDIV2 = PLL2_Div2-1; // 648 MHz / (1+1 ) = 324 MHz (the PHY DDR rate)
PLL2->PLLDIV2 |= (0x00008000); // Enable DDR divider
PLL2->PLLDIV1 |= (0x00008000); // Enable VPBE divider
PLL2->PLLCMD |= 0x00000001; // Tell PLL to do phase alignment
while ((PLL2->PLLSTAT) & 0x1); // Wait until done
waitloop(256*(PLL1_Mult/2));
PLL2->PLLCTL |= (0x00000008); // Take PLL out of reset
waitloop(2000*(PLL1_Mult/2)); // Wait for locking
PLL2->PLLCTL |= (0x00000001); // Switch out of bypass mode
}
int DDR2Init(void)
{
int32_t tempVTP;
/* Enable DDR2 module. */
LPSCTransition(LPSC_DDR2, PD0, PSC_ENABLE);
/* Setup the read latency (CAS Latency + 3 = 6 (but write 6-1=5)) */
DDR->DDRPHYCR = 0x14001900 | DDR_READ_Latency;
/* Set TIMUNLOCK bit, CAS Latency, number of banks, page size */
DDR->SDBCR = 0x00138000 |
(DDR_NM << 14) |
(DDR_CL << 9) |
(DDR_IBANK << 4) |
(DDR_PAGESIZE <<0);
// Program timing registers
DDR->SDTIMR = (DDR_T_RFC << 25) |
(DDR_T_RP << 22) |
(DDR_T_RCD << 19) |
(DDR_T_WR << 16) |
(DDR_T_RAS << 11) |
(DDR_T_RC << 6) |
(DDR_T_RRD << 3) |
(DDR_T_WTR << 0);
DDR->SDTIMR2 = (DDR_T_XSNR << 16) |
(DDR_T_XSRD << 8) |
(DDR_T_RTP << 5) |
(DDR_T_CKE << 0);
// Clear the TIMUNLOCK bit
DDR->SDBCR &= (~0x00008000);
// Set the refresh rate
DDR->SDRCR = DDR_RR;
// Dummy write/read to apply timing settings
DDRMem[0] = DDR_TEST_PATTERN;
if (DDRMem[0] == DDR_TEST_PATTERN)
UARTSendInt(DDRMem[0]);
// Set the DDR2 to syncreset
LPSCTransition(LPSC_DDR2, PD0, PSC_SYNCRESET);
// Set the DDR2 to enable
LPSCTransition(LPSC_DDR2, PD0, PSC_ENABLE);
/***************** DDR2 VTP Calibration ****************/
DDR->VTPIOCR = 0x201F; // Clear calibration start bit
DDR->VTPIOCR = 0xA01F; // Set calibration start bit
waitloop(11*33); // Wait for calibration to complete
SYSTEM->DDRVTPER = 0x1; // DDRVTPR Enable register
tempVTP = 0x3FF & DDRVTPR; // Read calibration data
// Write calibration data to VTP Control register
DDR->VTPIOCR = ((DDR->VTPIOCR) & 0xFFFFFC00) | tempVTP;
// Clear calibration enable bit
DDR->VTPIOCR = (DDR->VTPIOCR) & (~0x00002000);
// DDRVTPR Enable register - disable DDRVTPR access
SYSTEM->DDRVTPER = 0x0;
return E_PASS;
}
void DDR2Init()
{
Int32 tempVTP;
// Set the DDR2 to enable
LPSCTransition(LPSC_DDR2, PSC_ENABLE);
// For Micron MT47H64M16BT-37E @ 162 MHz
// Setup the read latency (CAS Latency + 3 = 6 (but write 6-1=5))
DDR->DDRPHYCR = (0x50006400) | DDR_READ_Latency;
// Set TIMUNLOCK bit, CAS LAtency 3, 8 banks, 1024-word page size
//DDR->SDBCR = 0x00138632;
DDR->SDBCR = 0x00138000 |
(DDR_NM << 14) |
(DDR_CL << 9) |
(DDR_IBANK << 4) |
(DDR_PAGESIZE <<0);
// Program timing registers
//DDR->SDTIMR = 0x28923211;
DDR->SDTIMR = (DDR_T_RFC << 25) |
(DDR_T_RP << 22) |
(DDR_T_RCD << 19) |
(DDR_T_WR << 16) |
(DDR_T_RAS << 11) |
(DDR_T_RC << 6) |
(DDR_T_RRD << 3) |
(DDR_T_WTR << 0);
//DDR->SDTIMR2 = 0x0016C722;
DDR->SDTIMR2 = (DDR_T_XSNR << 16) |
(DDR_T_XSRD << 8) |
(DDR_T_RTP << 5) |
(DDR_T_CKE << 0);
// Clear the TIMUNLOCK bit
DDR->SDBCR &= (~0x00008000);
// Set the refresh rate
DDR->SDRCR = DDR_RR;
// Dummy write/read to apply timing settings
DDRMem[0] = DDR_TEST_PATTERN;
if (DDRMem[0] == DDR_TEST_PATTERN)
UARTSendInt(DDRMem[0]);
// Set the DDR2 to syncreset
LPSCTransition(LPSC_DDR2, PSC_SYNCRESET);
// Set the DDR2 to enable
LPSCTransition(LPSC_DDR2, PSC_ENABLE);
/***************** DDR2 VTP Calibration ****************/
DDR->VTPIOCR = 0x201F; // Clear calibration start bit
DDR->VTPIOCR = 0xA01F; // Set calibration start bit
waitloop(11*33); // Wait for calibration to complete
SYSTEM->DDRVTPER = 0x1; // DDRVTPR Enable register
tempVTP = 0x3FF & DDRVTPR; // Read calibration data
// Write calibration data to VTP Control register
DDR->VTPIOCR = ((DDR->VTPIOCR) & 0xFFFFFC00) | tempVTP;
// Clear calibration enable bit
DDR->VTPIOCR = (DDR->VTPIOCR) & (~0x00002000);
// DDRVTPR Enable register - disable DDRVTPR access
SYSTEM->DDRVTPER = 0x0;
}
