static int fake_wbbus_probe(struct device *dev)
{
int ret;
char fwname[64];
/*
* load firmware with wishbone address map. In the real driver,
* we would first load the bitstream into the fpga and then read
* the header from its appropriate location.
*
* Below, we just use the PCI bus and slot number to get the firmware
* file.
*/
sprintf(fwname, "fakespec-%04x-%04x", spec_vendor, spec_device);
if ((ret = request_firmware(&wb_fw, fwname, dev)) != 0) {
pr_err(KBUILD_MODNAME ": failed to load "
"firmware \"%s\"\n", fwname);
return ret;
}
if ((ret = wb_register_bus(&fake_wb_bus)) < 0) {
goto bus_register_fail;
}
return 0;
bus_register_fail:
release_firmware(wb_fw);
return ret;
}
int spec_gennum_load(struct spec_dev *dev, const void *data, int size)
{
int i, done = 0, wrote = 0;
int err;
unsigned long j;
void __iomem *bar4 = dev->remap[2];
/* Ok, now call register access, which lived elsewhere */
wrote = gennum_loader(bar4, data, size);
if (wrote < 0)
return wrote;
j = jiffies + 2 * HZ;
while(!done) {
i = readl(bar4 + GN412X_FCL_IRQ);
if (i & 0x8) {
pr_info(KBUILD_MODNAME
": %s: done after %i\n", __func__,
wrote);
done = 1;
} else if( (i & 0x4) && !done) {
pr_info(KBUILD_MODNAME
": %s: error after %i\n", __func__,
wrote);
return -ETIMEDOUT;
}
if (time_after(jiffies, j)) {
pr_info(KBUILD_MODNAME
": %s: timeout after %i\n", __func__,
wrote);
return -ETIMEDOUT;
}
}
/*
* Register the device as a wishbone controller
*
* Here, we would in practice, read the location of the SDWB header
* from a register in PCI memory. For now we just use a demo firmware
* with the header information to test things out.
*/
dev->wb_bus.name = (char *)driver_name;
dev->wb_bus.owner = THIS_MODULE;
dev->wb_bus.ops = &spec_wb_ops;
/* The wb_cfggen tool sets the header base address to a default of 0 */
dev->wb_bus.sdwb_header_base = 0;
err = wb_register_bus(&dev->wb_bus);
if (err) {
pr_err(KBUILD_MODNAME ": failed to register wishbone bus\n");
return err;
}
dev->bus_registered = 1;
return 0;
}
