int wcn36xx_rx_skb(struct wcn36xx *wcn, struct sk_buff *skb)
{
struct ieee80211_rx_status status;
struct ieee80211_hdr *hdr;
struct wcn36xx_rx_bd *bd;
u16 fc, sn;
/*
* All fields must be 0, otherwise it can lead to
* unexpected consequences.
*/
memset(&status, 0, sizeof(status));
bd = (struct wcn36xx_rx_bd *)skb->data;
buff_to_be((u32 *)bd, sizeof(*bd)/sizeof(u32));
skb_put(skb, bd->pdu.mpdu_header_off + bd->pdu.mpdu_len);
skb_pull(skb, bd->pdu.mpdu_header_off);
status.mactime = 10;
status.freq = wcn->current_channel->center_freq;
status.band = wcn->current_channel->band;
status.signal = -RSSI0(bd);
status.antenna = 1;
status.rate_idx = 1;
status.flag = 0;
status.rx_flags = 0;
status.flag |= RX_FLAG_IV_STRIPPED |
RX_FLAG_MMIC_STRIPPED |
RX_FLAG_DECRYPTED;
wcn36xx_dbg(WCN36XX_DBG_RX, "status.flags=%x "
"status->vendor_radiotap_len=%x",
status.flag, status.vendor_radiotap_len);
memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
hdr = (struct ieee80211_hdr *) skb->data;
fc = __le16_to_cpu(hdr->frame_control);
sn = IEEE80211_SEQ_TO_SN(__le16_to_cpu(hdr->seq_ctrl));
if (ieee80211_is_beacon(hdr->frame_control)) {
wcn36xx_dbg(WCN36XX_DBG_BEACON, "beacon skb %p len %d fc %04x sn %d",
skb, skb->len, fc, sn);
wcn36xx_dbg_dump(WCN36XX_DBG_BEACON_DUMP, "SKB <<< ",
(char *)skb->data, skb->len);
} else {
wcn36xx_dbg(WCN36XX_DBG_RX, "rx skb %p len %d fc %04x sn %d",
skb, skb->len, fc, sn);
wcn36xx_dbg_dump(WCN36XX_DBG_RX_DUMP, "SKB <<< ",
(char *)skb->data, skb->len);
}
ieee80211_rx_ni(wcn->hw, skb);
return 0;
}
static int wcn36xx_smd_send_and_wait(struct wcn36xx *wcn, size_t len)
{
int avail;
init_completion(&wcn->smd_compl);
avail = smd_write_avail(wcn->smd_ch);
wcn36xx_dbg_dump(WCN36XX_DBG_SMD_DUMP, "SMD >>> ", wcn->smd_buf, len);
if (avail >= len) {
avail = smd_write(wcn->smd_ch, wcn->smd_buf, len);
if (avail != len) {
wcn36xx_error("Cannot write to SMD channel");
return -EAGAIN;
}
} else {
wcn36xx_error("SMD channel can accept only %d bytes", avail);
return -ENOMEM;
}
if (wait_for_completion_timeout(&wcn->smd_compl,
msecs_to_jiffies(SMD_MSG_TIMEOUT)) <= 0) {
wcn36xx_error("Timeout while waiting SMD response");
return -ETIME;
}
return 0;
}
static void wcn36xx_smd_rsp_process(struct wcn36xx *wcn, void *buf, size_t len)
{
struct wcn36xx_hal_msg_header *msg_header = buf;
wcn36xx_dbg_dump(WCN36XX_DBG_SMD_DUMP, "SMD <<< ", buf, len);
switch (msg_header->msg_type) {
case WCN36XX_HAL_START_RSP:
wcn36xx_smd_start_rsp(wcn, buf, len);
break;
case WCN36XX_HAL_CONFIG_STA_RSP:
wcn36xx_smd_config_sta_rsp(wcn, buf, len);
break;
case WCN36XX_HAL_CONFIG_BSS_RSP:
wcn36xx_smd_config_bss_rsp(wcn, buf, len);
break;
case WCN36XX_HAL_STOP_RSP:
case WCN36XX_HAL_ADD_STA_SELF_RSP:
wcn36xx_smd_add_sta_self_rsp(wcn, buf, len);
break;
case WCN36XX_HAL_DEL_STA_SELF_RSP:
case WCN36XX_HAL_DELETE_STA_RSP:
case WCN36XX_HAL_INIT_SCAN_RSP:
case WCN36XX_HAL_START_SCAN_RSP:
case WCN36XX_HAL_END_SCAN_RSP:
case WCN36XX_HAL_FINISH_SCAN_RSP:
case WCN36XX_HAL_DOWNLOAD_NV_RSP:
case WCN36XX_HAL_DELETE_BSS_RSP:
case WCN36XX_HAL_SEND_BEACON_RSP:
case WCN36XX_HAL_SET_LINK_ST_RSP:
case WCN36XX_HAL_UPDATE_PROBE_RSP_TEMPLATE_RSP:
case WCN36XX_HAL_SET_BSSKEY_RSP:
case WCN36XX_HAL_SET_STAKEY_RSP:
if (wcn36xx_smd_rsp_status_check(buf, len)) {
wcn36xx_warn("error response from hal request %d",
msg_header->msg_type);
}
break;
case WCN36XX_HAL_JOIN_RSP:
wcn36xx_smd_join_rsp(buf, len);
break;
case WCN36XX_HAL_UPDATE_SCAN_PARAM_RSP:
wcn36xx_smd_update_scan_params_rsp(buf, len);
break;
case WCN36XX_HAL_CH_SWITCH_RSP:
wcn36xx_smd_switch_channel_rsp(buf, len);
break;
case WCN36XX_HAL_OTA_TX_COMPL_IND:
wcn36xx_smd_tx_compl_ind(wcn, buf, len);
break;
default:
wcn36xx_error("SMD_EVENT (%d) not supported", msg_header->msg_type);
}
}
int wcn36xx_dxe_tx_frame(struct wcn36xx *wcn,
struct wcn36xx_vif *vif_priv,
struct sk_buff *skb,
bool is_low)
{
struct wcn36xx_dxe_ctl *ctl = NULL;
struct wcn36xx_dxe_desc *desc = NULL;
struct wcn36xx_dxe_ch *ch = NULL;
unsigned long flags;
ch = is_low ? &wcn->dxe_tx_l_ch : &wcn->dxe_tx_h_ch;
ctl = ch->head_blk_ctl;
spin_lock_irqsave(&ctl->next->skb_lock, flags);
/*
* If skb is not null that means that we reached the tail of the ring
* hence ring is full. Stop queues to let mac80211 back off until ring
* has an empty slot again.
*/
if (NULL != ctl->next->skb) {
ieee80211_stop_queues(wcn->hw);
wcn->queues_stopped = true;
spin_unlock_irqrestore(&ctl->next->skb_lock, flags);
return -EBUSY;
}
spin_unlock_irqrestore(&ctl->next->skb_lock, flags);
ctl->skb = NULL;
desc = ctl->desc;
/* Set source address of the BD we send */
desc->src_addr_l = ctl->bd_phy_addr;
desc->dst_addr_l = ch->dxe_wq;
desc->fr_len = sizeof(struct wcn36xx_tx_bd);
desc->ctrl = ch->ctrl_bd;
wcn36xx_dbg(WCN36XX_DBG_DXE, "DXE TX\n");
wcn36xx_dbg_dump(WCN36XX_DBG_DXE_DUMP, "DESC1 >>> ",
(char *)desc, sizeof(*desc));
wcn36xx_dbg_dump(WCN36XX_DBG_DXE_DUMP,
"BD >>> ", (char *)ctl->bd_cpu_addr,
sizeof(struct wcn36xx_tx_bd));
/* Set source address of the SKB we send */
ctl = ctl->next;
ctl->skb = skb;
desc = ctl->desc;
if (ctl->bd_cpu_addr) {
wcn36xx_err("bd_cpu_addr cannot be NULL for skb DXE\n");
return -EINVAL;
}
desc->src_addr_l = dma_map_single(NULL,
ctl->skb->data,
ctl->skb->len,
DMA_TO_DEVICE);
desc->dst_addr_l = ch->dxe_wq;
desc->fr_len = ctl->skb->len;
/* set dxe descriptor to VALID */
desc->ctrl = ch->ctrl_skb;
wcn36xx_dbg_dump(WCN36XX_DBG_DXE_DUMP, "DESC2 >>> ",
(char *)desc, sizeof(*desc));
wcn36xx_dbg_dump(WCN36XX_DBG_DXE_DUMP, "SKB >>> ",
(char *)ctl->skb->data, ctl->skb->len);
/* Move the head of the ring to the next empty descriptor */
ch->head_blk_ctl = ctl->next;
/*
* When connected and trying to send data frame chip can be in sleep
* mode and writing to the register will not wake up the chip. Instead
* notify chip about new frame through SMSM bus.
*/
if (is_low && vif_priv->pw_state == WCN36XX_BMPS) {
wcn->ctrl_ops->smsm_change_state(
0,
WCN36XX_SMSM_WLAN_TX_ENABLE);
} else {
/* indicate End Of Packet and generate interrupt on descriptor
* done.
*/
wcn36xx_dxe_write_register(wcn,
ch->reg_ctrl, ch->def_ctrl);
}
return 0;
}
static int wcn36xx_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
struct ieee80211_vif *vif,
struct ieee80211_sta *sta,
struct ieee80211_key_conf *key_conf)
{
struct wcn36xx *wcn = hw->priv;
struct wcn36xx_sta *sta_priv = (struct wcn36xx_sta *)sta->drv_priv;
int ret = 0;
u8 key[WLAN_MAX_KEY_LEN];
wcn36xx_dbg(WCN36XX_DBG_MAC, "mac80211 set key");
wcn36xx_dbg(WCN36XX_DBG_MAC, "Key: cmd=0x%x algo:0x%x, id:%d, len:%d flags 0x%x",
cmd, key_conf->cipher, key_conf->keyidx,
key_conf->keylen, key_conf->flags);
wcn36xx_dbg_dump(WCN36XX_DBG_MAC, "KEY: ",
key_conf->key,
key_conf->keylen);
switch (key_conf->cipher) {
case WLAN_CIPHER_SUITE_CCMP:
wcn->encrypt_type = WCN36XX_HAL_ED_CCMP;
break;
case WLAN_CIPHER_SUITE_TKIP:
wcn->encrypt_type = WCN36XX_HAL_ED_TKIP;
break;
default:
wcn36xx_error("Unsupported key type 0x%x",
key_conf->cipher);
ret = -EOPNOTSUPP;
goto out;
break;
}
switch (cmd) {
case SET_KEY:
if (WCN36XX_HAL_ED_TKIP == wcn->encrypt_type) {
/*
* Supplicant is sending key in the wrong order:
* Temporal Key (16 b) - TX MIC (8 b) - RX MIC (8 b)
* but HW expects it to be in the order as described in
* IEEE 802.11 spec (see chapter 11.7) like this:
* Temporal Key (16 b) - RX MIC (8 b) - TX MIC (8 b)
*/
memcpy(key, key_conf->key, 16);
memcpy(key + 16, key_conf->key + 24, 8);
memcpy(key + 24, key_conf->key + 16, 8);
} else {
memcpy(key, key_conf->key, key_conf->keylen);
}
if (IEEE80211_KEY_FLAG_PAIRWISE & key_conf->flags) {
sta_priv->is_data_encrypted = true;
/* Reconfigure bss with encrypt_type */
if (NL80211_IFTYPE_STATION == vif->type)
wcn36xx_smd_config_bss(wcn,
vif,
sta,
sta->addr,
true);
wcn36xx_smd_set_stakey(wcn,
wcn->encrypt_type,
key_conf->keyidx,
key_conf->keylen,
key,
get_sta_index(vif, sta_priv));
} else {
wcn36xx_smd_set_bsskey(wcn,
wcn->encrypt_type,
key_conf->keyidx,
key_conf->keylen,
key);
}
break;
case DISABLE_KEY:
if (!(IEEE80211_KEY_FLAG_PAIRWISE & key_conf->flags)) {
wcn36xx_smd_remove_bsskey(wcn,
wcn->encrypt_type,
key_conf->keyidx);
} else {
sta_priv->is_data_encrypted = false;
/* do not remove key if disassociated */
if (wcn->aid)
wcn36xx_smd_remove_stakey(wcn,
wcn->encrypt_type,
key_conf->keyidx,
get_sta_index(vif, sta_priv));
}
break;
default:
wcn36xx_error("Unsupported key cmd 0x%x", cmd);
ret = -EOPNOTSUPP;
goto out;
break;
}
out:
return ret;
}
int wcn36xx_dxe_tx_frame(struct wcn36xx *wcn,
struct sk_buff *skb,
bool is_low)
{
struct wcn36xx_dxe_ctl *ctl = NULL;
struct wcn36xx_dxe_desc *desc = NULL;
struct wcn36xx_dxe_ch *ch = NULL;
ch = is_low ? &wcn->dxe_tx_l_ch : &wcn->dxe_tx_h_ch;
ctl = ch->head_blk_ctl;
ctl->skb = NULL;
desc = ctl->desc;
/* Set source address of the BD we send */
desc->src_addr_l = ctl->bd_phy_addr;
desc->dst_addr_l = ch->dxe_wq;
desc->fr_len = sizeof(struct wcn36xx_tx_bd);
desc->ctrl = ch->ctrl_bd;
wcn36xx_dbg(WCN36XX_DBG_DXE, "DXE TX");
wcn36xx_dbg_dump(WCN36XX_DBG_DXE_DUMP, "DESC1 >>> ",
(char *)desc, sizeof(*desc));
wcn36xx_dbg_dump(WCN36XX_DBG_DXE_DUMP,
"BD >>> ", (char *)ctl->bd_cpu_addr,
sizeof(struct wcn36xx_tx_bd));
/* Set source address of the SKB we send */
ctl = ctl->next;
ctl->skb = skb;
desc = ctl->desc;
if (ctl->bd_cpu_addr) {
/* TODO: Recover from this situation */
wcn36xx_error("bd_cpu_addr cannot be NULL for skb DXE");
return -EINVAL;
}
desc->src_addr_l = dma_map_single(NULL,
ctl->skb->data,
ctl->skb->len,
DMA_TO_DEVICE);
desc->dst_addr_l = ch->dxe_wq;
desc->fr_len = ctl->skb->len;
/* set dxe descriptor to VALID */
desc->ctrl = ch->ctrl_skb;
wcn36xx_dbg_dump(WCN36XX_DBG_DXE_DUMP, "DESC2 >>> ",
(char *)desc, sizeof(*desc));
wcn36xx_dbg_dump(WCN36XX_DBG_DXE_DUMP, "SKB >>> ",
(char *)ctl->skb->data, ctl->skb->len);
/* Move the head of the ring to the next empty descriptor */
ch->head_blk_ctl = ctl->next;
/*
* When connected and trying to send data frame chip can be in sleep
* mode and writing to the register will not wake up the chip. Instead
* notify chip about new frame through SMSM bus.
*/
if (wcn->pw_state == WCN36XX_BMPS) {
smsm_change_state(SMSM_APPS_STATE,
0,
WCN36XX_SMSM_WLAN_TX_ENABLE);
} else {
/* indicate End Of Packet and generate interrupt on descriptor
* done.
*/
wcn36xx_dxe_write_register(wcn,
ch->reg_ctrl, ch->def_ctrl);
}
return 0;
}
int wcn36xx_dxe_tx_frame(struct wcn36xx *wcn,
struct wcn36xx_vif *vif_priv,
struct wcn36xx_tx_bd *bd,
struct sk_buff *skb,
bool is_low)
{
struct wcn36xx_dxe_desc *desc_bd, *desc_skb;
struct wcn36xx_dxe_ctl *ctl_bd, *ctl_skb;
struct wcn36xx_dxe_ch *ch = NULL;
unsigned long flags;
int ret;
ch = is_low ? &wcn->dxe_tx_l_ch : &wcn->dxe_tx_h_ch;
spin_lock_irqsave(&ch->lock, flags);
ctl_bd = ch->head_blk_ctl;
ctl_skb = ctl_bd->next;
/*
* If skb is not null that means that we reached the tail of the ring
* hence ring is full. Stop queues to let mac80211 back off until ring
* has an empty slot again.
*/
if (NULL != ctl_skb->skb) {
ieee80211_stop_queues(wcn->hw);
wcn->queues_stopped = true;
spin_unlock_irqrestore(&ch->lock, flags);
return -EBUSY;
}
if (unlikely(ctl_skb->bd_cpu_addr)) {
wcn36xx_err("bd_cpu_addr cannot be NULL for skb DXE\n");
ret = -EINVAL;
goto unlock;
}
desc_bd = ctl_bd->desc;
desc_skb = ctl_skb->desc;
ctl_bd->skb = NULL;
/* write buffer descriptor */
memcpy(ctl_bd->bd_cpu_addr, bd, sizeof(*bd));
/* Set source address of the BD we send */
desc_bd->src_addr_l = ctl_bd->bd_phy_addr;
desc_bd->dst_addr_l = ch->dxe_wq;
desc_bd->fr_len = sizeof(struct wcn36xx_tx_bd);
wcn36xx_dbg(WCN36XX_DBG_DXE, "DXE TX\n");
wcn36xx_dbg_dump(WCN36XX_DBG_DXE_DUMP, "DESC1 >>> ",
(char *)desc_bd, sizeof(*desc_bd));
wcn36xx_dbg_dump(WCN36XX_DBG_DXE_DUMP,
"BD >>> ", (char *)ctl_bd->bd_cpu_addr,
sizeof(struct wcn36xx_tx_bd));
desc_skb->src_addr_l = dma_map_single(wcn->dev,
skb->data,
skb->len,
DMA_TO_DEVICE);
if (dma_mapping_error(wcn->dev, desc_skb->src_addr_l)) {
dev_err(wcn->dev, "unable to DMA map src_addr_l\n");
ret = -ENOMEM;
goto unlock;
}
ctl_skb->skb = skb;
desc_skb->dst_addr_l = ch->dxe_wq;
desc_skb->fr_len = ctl_skb->skb->len;
wcn36xx_dbg_dump(WCN36XX_DBG_DXE_DUMP, "DESC2 >>> ",
(char *)desc_skb, sizeof(*desc_skb));
wcn36xx_dbg_dump(WCN36XX_DBG_DXE_DUMP, "SKB >>> ",
(char *)ctl_skb->skb->data, ctl_skb->skb->len);
/* Move the head of the ring to the next empty descriptor */
ch->head_blk_ctl = ctl_skb->next;
/* Commit all previous writes and set descriptors to VALID */
wmb();
desc_skb->ctrl = ch->ctrl_skb;
wmb();
desc_bd->ctrl = ch->ctrl_bd;
/*
* When connected and trying to send data frame chip can be in sleep
* mode and writing to the register will not wake up the chip. Instead
* notify chip about new frame through SMSM bus.
*/
if (is_low && vif_priv->pw_state == WCN36XX_BMPS) {
qcom_smem_state_update_bits(wcn->tx_rings_empty_state,
WCN36XX_SMSM_WLAN_TX_ENABLE,
WCN36XX_SMSM_WLAN_TX_ENABLE);
} else {
/* indicate End Of Packet and generate interrupt on descriptor
* done.
*/
wcn36xx_dxe_write_register(wcn,
ch->reg_ctrl, ch->def_ctrl);
}
ret = 0;
unlock:
spin_unlock_irqrestore(&ch->lock, flags);
return ret;
}
