static int
acer_pci_intr(void *arg)
{
struct pciide_softc *sc = arg;
struct pciide_channel *cp;
struct ata_channel *wdc_cp;
int i, rv, crv;
u_int32_t chids;
rv = 0;
chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS);
for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
cp = &sc->pciide_channels[i];
wdc_cp = &cp->ata_channel;
/* If a compat channel skip. */
if (cp->compat)
continue;
if (chids & ACER_CHIDS_INT(i)) {
crv = wdcintr(wdc_cp);
if (crv == 0) {
aprint_error("%s:%d: bogus intr\n",
device_xname(
sc->sc_wdcdev.sc_atac.atac_dev), i);
pciide_irqack(wdc_cp);
} else
rv = 1;
}
}
return rv;
}
static int
cmd_pci_intr(void *arg)
{
struct pciide_softc *sc = arg;
struct pciide_channel *cp;
struct wdc_channel *wdc_cp;
int i, rv, crv;
u_int32_t priirq, secirq;
rv = 0;
priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF);
secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23);
for (i = 0; i < sc->sc_wdcdev.nchannels; i++) {
cp = &sc->pciide_channels[i];
wdc_cp = &cp->wdc_channel;
/* If a compat channel skip. */
if (cp->compat)
continue;
if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) ||
(i == 1 && (secirq & CMD_ARTTIM23_IRQ))) {
crv = wdcintr(wdc_cp);
if (crv == 0)
printf("%s:%d: bogus intr\n",
sc->sc_wdcdev.sc_dev.dv_xname, i);
else
rv = 1;
}
}
return rv;
}
static int
serverworkscsb6_pci_intr(void *arg)
{
struct pciide_softc *sc = arg;
struct pciide_channel *cp;
struct ata_channel *wdc_cp;
int rv = 0;
int i, crv;
for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
cp = &sc->pciide_channels[i];
wdc_cp = &cp->ata_channel;
/*
* The CSB6 doesn't assert IDEDMA_CTL_INTR for non-DMA commands.
* Until we find a way to know if the controller posted an
* interrupt, always call wdcintr(), which will try to guess
* if the interrupt was for us or not (and checks
* IDEDMA_CTL_INTR for DMA commands only).
*/
crv = wdcintr(wdc_cp);
if (crv != 0)
rv = 1;
}
return rv;
}
static int
serverworks_pci_intr(void *arg)
{
struct pciide_softc *sc = arg;
struct pciide_channel *cp;
struct ata_channel *wdc_cp;
int rv = 0;
int dmastat, i, crv;
for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
cp = &sc->pciide_channels[i];
dmastat = bus_space_read_1(sc->sc_dma_iot,
cp->dma_iohs[IDEDMA_CTL], 0);
if ((dmastat & (IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) !=
IDEDMA_CTL_INTR)
continue;
wdc_cp = &cp->ata_channel;
crv = wdcintr(wdc_cp);
if (crv == 0) {
aprint_error("%s:%d: bogus intr\n",
device_xname(sc->sc_wdcdev.sc_atac.atac_dev), i);
bus_space_write_1(sc->sc_dma_iot,
cp->dma_iohs[IDEDMA_CTL], 0, dmastat);
} else
rv = 1;
}
return rv;
}
/*
* Podule interrupt handler
*
* If the interrupt was from our card pass it on to the wdc interrupt handler
*/
int
simide_intr(void *arg)
{
struct simide_channel *scp = arg;
irqhandler_t *ihp = &scp->sc_ih;
volatile u_char *intraddr = (volatile u_char *)ihp->ih_maskaddr;
/* XXX - not bus space yet - should really be handled by podulebus */
if ((*intraddr) & ihp->ih_maskbits)
wdcintr(&scp->sc_channel);
return(0);
}
int
rapide_intr(void *arg)
{
struct rapide_channel *rcp = arg;
irqhandler_t *ihp = &rcp->rc_ih;
volatile u_char *intraddr = (volatile u_char *)ihp->ih_maskaddr;
/* XXX - Issue 1 cards will need to clear the interrupt */
/* XXX - not bus space yet - should really be handled by podulebus */
if ((*intraddr) & ihp->ih_maskbits)
wdcintr(&rcp->rc_channel);
return(0);
}
int
wdc_amiga_intr(void *arg)
{
struct wdc_amiga_softc *sc;
uint8_t intreq;
int ret;
sc = (struct wdc_amiga_softc *)arg;
ret = 0;
intreq = gayle_intr_status();
if (intreq & GAYLE_INT_IDE) {
if (!is_a4000())
gayle_intr_ack(0x7C | (intreq & GAYLE_INT_IDEACK));
ret = wdcintr(&sc->sc_channel);
}
return ret;
}
int
wdc_buddha_intr(void *arg)
{
struct wdc_buddha_softc *sc = (struct wdc_buddha_softc *)arg;
int nchannels, i, ret;
volatile char *p;
ret = 0;
nchannels = sc->sc_wdcdev.sc_atac.atac_nchannels;
p = sc->ba;
for (i=0; i<nchannels; i++) {
if (p[0xf00 + 0x40*i] & 0x80) {
wdcintr(&sc->channels[i]);
ret = 1;
}
}
return ret;
}
