static int wdt_open(struct inode *inode, struct file *file) { switch(minor(inode->i_rdev)) { case WATCHDOG_MINOR: if(test_and_set_bit(0, &wdt_is_open)) return -EBUSY; /* * Activate */ inb_p(WDT_DC); /* Disable */ wdt_ctr_mode(0,3); wdt_ctr_mode(1,2); wdt_ctr_mode(2,0); wdt_ctr_load(0, 8948); /* count at 100Hz */ wdt_ctr_load(1,WD_TIMO); /* Timeout 120 seconds */ wdt_ctr_load(2,65535); outb_p(0, WDT_DC); /* Enable */ return 0; case TEMP_MINOR: return 0; default: return -ENODEV; } }
static int wdt_open(struct inode *inode, struct file *file) { switch(MINOR(inode->i_rdev)) { case WATCHDOG_MINOR: if(wdt_is_open) return -EBUSY; MOD_INC_USE_COUNT; /* * Activate */ wdt_is_open=1; inb_p(WDT_DC); /* Disable */ wdt_ctr_mode(0,3); wdt_ctr_mode(1,2); wdt_ctr_mode(2,0); wdt_ctr_load(0, 8948); /* count at 100Hz */ wdt_ctr_load(1,WD_TIMO); /* Timeout 120 seconds */ wdt_ctr_load(2,65535); outb_p(0, WDT_DC); /* Enable */ return 0; case TEMP_MINOR: MOD_INC_USE_COUNT; return 0; default: return -ENODEV; } }
static void wdt_ping(void) { /* Write a watchdog value */ inb_p(WDT_DC); wdt_ctr_mode(1,2); wdt_ctr_load(1,WD_TIMO); /* Timeout */ outb_p(0, WDT_DC); }
static int wdt_start(void) { unsigned long flags; spin_lock_irqsave(&wdt_lock, flags); inb_p(WDT_DC); /* Disable watchdog */ wdt_ctr_mode(0, 3); /* Program CTR0 for Mode 3: Square Wave Generator */ wdt_ctr_mode(1, 2); /* Program CTR1 for Mode 2: Rate Generator */ wdt_ctr_mode(2, 0); /* Program CTR2 for Mode 0: Pulse on Terminal Count */ wdt_ctr_load(0, 8948); /* Count at 100Hz */ wdt_ctr_load(1, wd_heartbeat); /* Heartbeat */ wdt_ctr_load(2, 65535); /* Length of reset pulse */ outb_p(0, WDT_DC); /* Enable watchdog */ spin_unlock_irqrestore(&wdt_lock, flags); return 0; }
static int wdt_write(struct inode *inode, struct file *file, const char *buf, int count) { /* Write a watchdog value */ inb_p(WDT_DC); wdt_ctr_mode(1,2); wdt_ctr_load(1,WD_TIMO); /* Timeout */ outb_p(0, WDT_DC); return count; }
static void wdt_ping(void) { unsigned long flags; spin_lock_irqsave(&wdt_lock, flags); /* Write a watchdog value */ inb_p(WDT_DC); /* Disable watchdog */ wdt_ctr_mode(1, 2); /* Re-Program CTR1 for Mode 2: Rate Generator */ wdt_ctr_load(1, wd_heartbeat); /* Heartbeat */ outb_p(0, WDT_DC); /* Enable watchdog */ spin_unlock_irqrestore(&wdt_lock, flags); }