static int wm8350_dcdc_set_suspend_enable(struct regulator_dev *rdev)
{
struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
int dcdc = rdev_get_id(rdev);
u16 val;
switch (dcdc) {
case WM8350_DCDC_1:
val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER)
& ~WM8350_DCDC_HIB_MODE_MASK;
wm8350_reg_write(wm8350, WM8350_DCDC1_LOW_POWER,
val | wm8350->pmic.dcdc1_hib_mode);
break;
case WM8350_DCDC_3:
val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER)
& ~WM8350_DCDC_HIB_MODE_MASK;
wm8350_reg_write(wm8350, WM8350_DCDC3_LOW_POWER,
val | wm8350->pmic.dcdc3_hib_mode);
break;
case WM8350_DCDC_4:
val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER)
& ~WM8350_DCDC_HIB_MODE_MASK;
wm8350_reg_write(wm8350, WM8350_DCDC4_LOW_POWER,
val | wm8350->pmic.dcdc4_hib_mode);
break;
case WM8350_DCDC_6:
val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER)
& ~WM8350_DCDC_HIB_MODE_MASK;
wm8350_reg_write(wm8350, WM8350_DCDC6_LOW_POWER,
val | wm8350->pmic.dcdc6_hib_mode);
break;
case WM8350_DCDC_2:
case WM8350_DCDC_5:
default:
return -EINVAL;
}
return 0;
}
static int wm8350_ldo_set_voltage(struct regulator_dev *rdev, int min_uV,
int max_uV, unsigned *selector)
{
struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
int volt_reg, ldo = rdev_get_id(rdev), mV, min_mV = min_uV / 1000,
max_mV = max_uV / 1000;
u16 val;
if (min_mV < 900 || min_mV > 3300)
return -EINVAL;
if (max_mV < 900 || max_mV > 3300)
return -EINVAL;
if (min_mV < 1800) {
/* step size is 50mV < 1800mV */
mV = (min_mV - 851) / 50;
if (wm8350_ldo_val_to_mvolts(mV) > max_mV)
return -EINVAL;
BUG_ON(wm8350_ldo_val_to_mvolts(mV) < min_mV);
} else {
/* step size is 100mV > 1800mV */
mV = ((min_mV - 1701) / 100) + 16;
if (wm8350_ldo_val_to_mvolts(mV) > max_mV)
return -EINVAL;
BUG_ON(wm8350_ldo_val_to_mvolts(mV) < min_mV);
}
switch (ldo) {
case WM8350_LDO_1:
volt_reg = WM8350_LDO1_CONTROL;
break;
case WM8350_LDO_2:
volt_reg = WM8350_LDO2_CONTROL;
break;
case WM8350_LDO_3:
volt_reg = WM8350_LDO3_CONTROL;
break;
case WM8350_LDO_4:
volt_reg = WM8350_LDO4_CONTROL;
break;
default:
return -EINVAL;
}
*selector = mV;
/* all LDOs have same mV bits */
val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_VSEL_MASK;
wm8350_reg_write(wm8350, volt_reg, val | mV);
return 0;
}
static ssize_t show_headphone(struct device_driver *dev, char *buf)
{
struct imx_3stack_priv *priv = &machine_priv;
u16 reg;
reg = wm8350_reg_read(priv->wm8350, WM8350_JACK_PIN_STATUS);
if (reg & WM8350_JACK_R_LVL)
strcpy(buf, "speaker\n");
else
strcpy(buf, "headphone\n");
return strlen(buf);
}
static int wm8350_wdt_kick(struct wm8350 *wm8350)
{
int ret;
u16 reg;
mutex_lock(&wdt_mutex);
reg = wm8350_reg_read(wm8350, WM8350_SYSTEM_CONTROL_2);
ret = wm8350_reg_write(wm8350, WM8350_SYSTEM_CONTROL_2, reg);
mutex_unlock(&wdt_mutex);
return ret;
}
static int wm8350_charger_config(struct wm8350 *wm8350,
struct wm8350_charger_policy *policy)
{
u16 reg, eoc_mA, fast_limit_mA;
if (!policy) {
dev_warn(wm8350->dev,
"No charger policy, charger not configured.\n");
return -EINVAL;
}
/* make sure USB fast charge current is not > 500mA */
if (policy->fast_limit_USB_mA > 500) {
dev_err(wm8350->dev, "USB fast charge > 500mA\n");
return -EINVAL;
}
eoc_mA = WM8350_CHG_EOC_mA(policy->eoc_mA);
wm8350_reg_unlock(wm8350);
reg = wm8350_reg_read(wm8350, WM8350_BATTERY_CHARGER_CONTROL_1)
& WM8350_CHG_ENA_R168;
wm8350_reg_write(wm8350, WM8350_BATTERY_CHARGER_CONTROL_1,
reg | eoc_mA | policy->trickle_start_mV |
WM8350_CHG_TRICKLE_TEMP_CHOKE |
WM8350_CHG_TRICKLE_USB_CHOKE |
WM8350_CHG_FAST_USB_THROTTLE);
if (wm8350_get_supplies(wm8350) & WM8350_USB_SUPPLY) {
fast_limit_mA =
WM8350_CHG_FAST_LIMIT_mA(policy->fast_limit_USB_mA);
wm8350_reg_write(wm8350, WM8350_BATTERY_CHARGER_CONTROL_2,
policy->charge_mV | policy->trickle_charge_USB_mA |
fast_limit_mA | wm8350_charge_time_min(wm8350,
policy->charge_timeout));
} else {
fast_limit_mA =
WM8350_CHG_FAST_LIMIT_mA(policy->fast_limit_mA);
wm8350_reg_write(wm8350, WM8350_BATTERY_CHARGER_CONTROL_2,
policy->charge_mV | policy->trickle_charge_mA |
fast_limit_mA | wm8350_charge_time_min(wm8350,
policy->charge_timeout));
}
wm8350_reg_lock(wm8350);
return 0;
}
static int wm8350_dcdc25_set_suspend_disable(struct regulator_dev *rdev)
{
struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
int dcdc = rdev_get_id(rdev);
u16 val;
switch (dcdc) {
case WM8350_DCDC_2:
val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL)
& ~WM8350_DC2_HIB_MODE_MASK;
wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val |
(WM8350_DC2_HIB_MODE_DISABLE << WM8350_DC2_HIB_MODE_SHIFT));
break;
case WM8350_DCDC_5:
val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL)
& ~WM8350_DC5_HIB_MODE_MASK;
wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val |
(WM8350_DC5_HIB_MODE_DISABLE << WM8350_DC5_HIB_MODE_SHIFT));
break;
default:
return -EINVAL;
}
return 0;
}
static int wm8350_wdt_ping(struct watchdog_device *wdt_dev)
{
struct wm8350 *wm8350 = watchdog_get_drvdata(wdt_dev);
int ret;
u16 reg;
mutex_lock(&wdt_mutex);
reg = wm8350_reg_read(wm8350, WM8350_SYSTEM_CONTROL_2);
ret = wm8350_reg_write(wm8350, WM8350_SYSTEM_CONTROL_2, reg);
mutex_unlock(&wdt_mutex);
return ret;
}
static int wm8350_bat_check_health(struct wm8350 *wm8350)
{
u16 reg;
if (wm8350_read_battery_uvolts(wm8350) < 2850000)
return POWER_SUPPLY_HEALTH_UNSPEC_FAILURE;
reg = wm8350_reg_read(wm8350, WM8350_CHARGER_OVERRIDES);
if (reg & WM8350_CHG_BATT_HOT_OVRDE)
return POWER_SUPPLY_HEALTH_OVERHEAT;
if (reg & WM8350_CHG_BATT_COLD_OVRDE)
return POWER_SUPPLY_HEALTH_COLD;
return POWER_SUPPLY_HEALTH_GOOD;
}
static int wm8350_wdt_stop(struct wm8350 *wm8350)
{
int ret;
u16 reg;
mutex_lock(&wdt_mutex);
wm8350_reg_unlock(wm8350);
reg = wm8350_reg_read(wm8350, WM8350_SYSTEM_CONTROL_2);
reg &= ~WM8350_WDOG_MODE_MASK;
ret = wm8350_reg_write(wm8350, WM8350_SYSTEM_CONTROL_2, reg);
wm8350_reg_lock(wm8350);
mutex_unlock(&wdt_mutex);
return ret;
}
static int wm8350_rtc_set_pie(struct wm8350_rtc *wm_rtc, unsigned long freq)
{
struct wm8350 *wm8350 = to_wm8350_from_rtc(wm_rtc);
int ret, power;
u16 reg;
power = ffs(freq);
if ((power == fls(freq)) && freq < 1025) {
wm_rtc->pie_freq = freq;
reg = wm8350_reg_read(wm8350, WM8350_RTC_TIME_CONTROL);
reg &= ~WM8350_RTC_DSW_MASK;
reg |= (power + 1) << WM8350_RTC_DSW_SHIFT;
ret = wm8350_reg_write(wm8350, WM8350_RTC_TIME_CONTROL, reg);
return ret;
}
return -EINVAL;
}
static int wm8350_bat_get_charge_type(struct wm8350 *wm8350)
{
int state;
state = wm8350_reg_read(wm8350, WM8350_BATTERY_CHARGER_CONTROL_2) &
WM8350_CHG_STS_MASK;
switch (state) {
case WM8350_CHG_STS_OFF:
return POWER_SUPPLY_CHARGE_TYPE_NONE;
case WM8350_CHG_STS_TRICKLE:
return POWER_SUPPLY_CHARGE_TYPE_TRICKLE;
case WM8350_CHG_STS_FAST:
return POWER_SUPPLY_CHARGE_TYPE_FAST;
default:
return POWER_SUPPLY_CHARGE_TYPE_UNKNOWN;
}
}
int wm8350_dcdc_set_slot(struct wm8350 *wm8350, int dcdc, u16 start,
u16 stop, u16 fault)
{
int slot_reg;
u16 val;
dev_dbg(wm8350->dev, "%s %d start %d stop %d\n",
__func__, dcdc, start, stop);
/* slot valid ? */
if (start > 15 || stop > 15)
return -EINVAL;
switch (dcdc) {
case WM8350_DCDC_1:
slot_reg = WM8350_DCDC1_TIMEOUTS;
break;
case WM8350_DCDC_2:
slot_reg = WM8350_DCDC2_TIMEOUTS;
break;
case WM8350_DCDC_3:
slot_reg = WM8350_DCDC3_TIMEOUTS;
break;
case WM8350_DCDC_4:
slot_reg = WM8350_DCDC4_TIMEOUTS;
break;
case WM8350_DCDC_5:
slot_reg = WM8350_DCDC5_TIMEOUTS;
break;
case WM8350_DCDC_6:
slot_reg = WM8350_DCDC6_TIMEOUTS;
break;
default:
return -EINVAL;
}
val = wm8350_reg_read(wm8350, slot_reg) &
~(WM8350_DC1_ENSLOT_MASK | WM8350_DC1_SDSLOT_MASK |
WM8350_DC1_ERRACT_MASK);
wm8350_reg_write(wm8350, slot_reg,
val | (start << WM8350_DC1_ENSLOT_SHIFT) |
(stop << WM8350_DC1_SDSLOT_SHIFT) |
(fault << WM8350_DC1_ERRACT_SHIFT));
return 0;
}
/*
* Set current time and date in RTC
*/
static int wm8350_rtc_settime(struct device *dev, struct rtc_time *tm)
{
struct wm8350_rtc *wm_rtc = to_wm8350_rtc_device(dev);
struct wm8350 *wm8350 = to_wm8350_from_rtc(wm_rtc);
u16 time[4];
u16 rtc_ctrl;
int ret, retries = WM8350_SET_TIME_RETRIES;
dbg("%s tm->tm_wday %d, tm->tm_mon %d",
__FUNCTION__, tm->tm_wday, tm->tm_mon);
time[0] = tm->tm_sec;
time[0] |= tm->tm_min << WM8350_RTC_MINS_SHIFT;
time[1] = tm->tm_hour;
time[1] |= (tm->tm_wday + 1) << WM8350_RTC_DAY_SHIFT;
time[2] = tm->tm_mday;
time[2] |= (tm->tm_mon + 1) << WM8350_RTC_MTH_SHIFT;
time[3] = ((tm->tm_year + 1900) / 100) << WM8350_RTC_YHUNDREDS_SHIFT;
time[3] |= (tm->tm_year + 1900) % 100;
/* Set RTC_SET to stop the clock */
ret = wm8350_set_bits(wm8350, WM8350_RTC_TIME_CONTROL, WM8350_RTC_SET);
if (ret < 0)
return ret;
/* Wait until confirmation of stopping */
do {
rtc_ctrl = wm8350_reg_read(wm8350, WM8350_RTC_TIME_CONTROL);
schedule_timeout_interruptible(msecs_to_jiffies(1));
} while (retries-- && !(rtc_ctrl & WM8350_RTC_STS));
if (!retries) {
printk(KERN_ERR "wm8350-rtc time out on set confirmation\n");
return -EIO;
}
/* Write time to RTC */
ret = wm8350_block_write(wm8350, WM8350_RTC_SECONDS_MINUTES, 4, time);
if (ret < 0)
return ret;
/* Clear RTC_SET to start the clock */
ret = wm8350_clear_bits(wm8350, WM8350_RTC_TIME_CONTROL,
WM8350_RTC_SET);
return ret;
}
/*
* Set current time and date in RTC
*/
static int wm8350_rtc_settime(struct device *dev, struct rtc_time *tm)
{
struct wm8350 *wm8350 = dev_get_drvdata(dev);
u16 time[4];
u16 rtc_ctrl;
int ret, retries = WM8350_SET_TIME_RETRIES;
time[0] = tm->tm_sec;
time[0] |= tm->tm_min << WM8350_RTC_MINS_SHIFT;
time[1] = tm->tm_hour;
time[1] |= (tm->tm_wday + 1) << WM8350_RTC_DAY_SHIFT;
time[2] = tm->tm_mday;
time[2] |= (tm->tm_mon + 1) << WM8350_RTC_MTH_SHIFT;
time[3] = ((tm->tm_year + 1900) / 100) << WM8350_RTC_YHUNDREDS_SHIFT;
time[3] |= (tm->tm_year + 1900) % 100;
dev_dbg(dev, "Setting: %04x %04x %04x %04x\n",
time[0], time[1], time[2], time[3]);
/* Set RTC_SET to stop the clock */
ret = wm8350_set_bits(wm8350, WM8350_RTC_TIME_CONTROL, WM8350_RTC_SET);
if (ret < 0)
return ret;
/* Wait until confirmation of stopping */
do {
rtc_ctrl = wm8350_reg_read(wm8350, WM8350_RTC_TIME_CONTROL);
schedule_timeout_uninterruptible(msecs_to_jiffies(1));
} while (--retries && !(rtc_ctrl & WM8350_RTC_STS));
if (!retries) {
dev_err(dev, "timed out on set confirmation\n");
return -EIO;
}
/* Write time to RTC */
ret = wm8350_block_write(wm8350, WM8350_RTC_SECONDS_MINUTES, 4, time);
if (ret < 0)
return ret;
/* Clear RTC_SET to start the clock */
ret = wm8350_clear_bits(wm8350, WM8350_RTC_TIME_CONTROL,
WM8350_RTC_SET);
return ret;
}
static int wm8350_dcdc_set_voltage(struct regulator_dev *rdev, int min_uV,
int max_uV, unsigned *selector)
{
struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
int volt_reg, dcdc = rdev_get_id(rdev), mV,
min_mV = min_uV / 1000, max_mV = max_uV / 1000;
u16 val;
if (min_mV < 850 || min_mV > 4025)
return -EINVAL;
if (max_mV < 850 || max_mV > 4025)
return -EINVAL;
/* step size is 25mV */
mV = (min_mV - 826) / 25;
if (wm8350_dcdc_val_to_mvolts(mV) > max_mV)
return -EINVAL;
BUG_ON(wm8350_dcdc_val_to_mvolts(mV) < min_mV);
switch (dcdc) {
case WM8350_DCDC_1:
volt_reg = WM8350_DCDC1_CONTROL;
break;
case WM8350_DCDC_3:
volt_reg = WM8350_DCDC3_CONTROL;
break;
case WM8350_DCDC_4:
volt_reg = WM8350_DCDC4_CONTROL;
break;
case WM8350_DCDC_6:
volt_reg = WM8350_DCDC6_CONTROL;
break;
case WM8350_DCDC_2:
case WM8350_DCDC_5:
default:
return -EINVAL;
}
*selector = mV;
/* all DCDCs have same mV bits */
val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_DC1_VSEL_MASK;
wm8350_reg_write(wm8350, volt_reg, val | mV);
return 0;
}
static int wm8350_rtc_suspend(struct platform_device *pdev, pm_message_t state)
{
struct wm8350 *wm8350 = dev_get_drvdata(&pdev->dev);
int ret = 0;
u16 reg;
reg = wm8350_reg_read(wm8350, WM8350_RTC_TIME_CONTROL);
if (device_may_wakeup(&wm8350->rtc.pdev->dev) &&
reg & WM8350_RTC_ALMSTS) {
ret = wm8350_rtc_stop_alarm(wm8350);
if (ret != 0)
dev_err(&pdev->dev, "Failed to stop RTC alarm: %d\n",
ret);
}
return ret;
}
static int wm8350_wdt_stop(struct watchdog_device *wdt_dev)
{
struct wm8350 *wm8350 = watchdog_get_drvdata(wdt_dev);
int ret;
u16 reg;
mutex_lock(&wdt_mutex);
wm8350_reg_unlock(wm8350);
reg = wm8350_reg_read(wm8350, WM8350_SYSTEM_CONTROL_2);
reg &= ~WM8350_WDOG_MODE_MASK;
ret = wm8350_reg_write(wm8350, WM8350_SYSTEM_CONTROL_2, reg);
wm8350_reg_lock(wm8350);
mutex_unlock(&wdt_mutex);
return ret;
}
static irqreturn_t wm8350_mic_handler(int irq, void *data)
{
struct wm8350_data *priv = data;
struct wm8350 *wm8350 = priv->codec.control_data;
u16 reg;
int report = 0;
reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
if (reg & WM8350_JACK_MICSCD_LVL)
report |= priv->mic.short_report;
if (reg & WM8350_JACK_MICSD_LVL)
report |= priv->mic.report;
snd_soc_jack_report(priv->mic.jack, report,
priv->mic.report | priv->mic.short_report);
return IRQ_HANDLED;
}
static int wm8350_wdt_set_timeout(struct wm8350 *wm8350, u16 value)
{
int ret;
u16 reg;
mutex_lock(&wdt_mutex);
wm8350_reg_unlock(wm8350);
reg = wm8350_reg_read(wm8350, WM8350_SYSTEM_CONTROL_2);
reg &= ~WM8350_WDOG_TO_MASK;
reg |= value;
ret = wm8350_reg_write(wm8350, WM8350_SYSTEM_CONTROL_2, reg);
wm8350_reg_lock(wm8350);
mutex_unlock(&wdt_mutex);
return ret;
}
static int wm8350_batt_status(struct wm8350 *wm8350)
{
u16 state;
state = wm8350_reg_read(wm8350, WM8350_BATTERY_CHARGER_CONTROL_2);
state &= WM8350_CHG_STS_MASK;
switch (state) {
case WM8350_CHG_STS_OFF:
return POWER_SUPPLY_STATUS_DISCHARGING;
case WM8350_CHG_STS_TRICKLE:
case WM8350_CHG_STS_FAST:
return POWER_SUPPLY_STATUS_CHARGING;
default:
return POWER_SUPPLY_STATUS_UNKNOWN;
}
}
static irqreturn_t wm8350_hp_jack_handler(int irq, void *data)
{
struct wm8350_data *priv = data;
struct wm8350 *wm8350 = priv->codec.control_data;
u16 reg;
int report;
int mask;
struct wm8350_jack_data *jack = NULL;
switch (irq - wm8350->irq_base) {
case WM8350_IRQ_CODEC_JCK_DET_L:
jack = &priv->hpl;
mask = WM8350_JACK_L_LVL;
break;
case WM8350_IRQ_CODEC_JCK_DET_R:
jack = &priv->hpr;
mask = WM8350_JACK_R_LVL;
break;
default:
BUG();
}
if (!jack->jack) {
dev_warn(wm8350->dev, "Jack interrupt called with no jack\n");
return IRQ_NONE;
}
/* Debounce */
msleep(200);
reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
if (reg & mask)
report = jack->report;
else
report = 0;
snd_soc_jack_report(jack->jack, report, jack->report);
return IRQ_HANDLED;
}
static int wm8350_dcdc_set_suspend_voltage(struct regulator_dev *rdev, int uV)
{
struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
int volt_reg, mV = uV / 1000, dcdc = rdev_get_id(rdev);
u16 val;
dev_dbg(wm8350->dev, "%s %d mV %d\n", __func__, dcdc, mV);
if (mV && (mV < 850 || mV > 4025)) {
dev_err(wm8350->dev,
"DCDC%d suspend voltage %d mV out of range\n",
dcdc, mV);
return -EINVAL;
}
if (mV == 0)
mV = 850;
switch (dcdc) {
case WM8350_DCDC_1:
volt_reg = WM8350_DCDC1_LOW_POWER;
break;
case WM8350_DCDC_3:
volt_reg = WM8350_DCDC3_LOW_POWER;
break;
case WM8350_DCDC_4:
volt_reg = WM8350_DCDC4_LOW_POWER;
break;
case WM8350_DCDC_6:
volt_reg = WM8350_DCDC6_LOW_POWER;
break;
case WM8350_DCDC_2:
case WM8350_DCDC_5:
default:
return -EINVAL;
}
/* all DCDCs have same mV bits */
val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_DC1_VSEL_MASK;
wm8350_reg_write(wm8350, volt_reg,
val | wm8350_dcdc_mvolts_to_val(mV));
return 0;
}
/*
* Set alarm time and date in RTC
*/
static int wm8350_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct wm8350_rtc *wm_rtc = to_wm8350_rtc_device(dev);
struct wm8350 *wm8350 = to_wm8350_from_rtc(wm_rtc);
struct rtc_time *tm = &alrm->time;
u16 rtc_ctrl;
u16 time[3];
int ret, retries = WM8350_SET_ALM_RETRIES;
time[0] = tm->tm_sec;
time[0] |= tm->tm_min << WM8350_RTC_ALMMINS_SHIFT;
time[1] = tm->tm_hour;
time[1] |= WM8350_RTC_ALMDAY_MASK;
time[2] = WM8350_RTC_ALMDATE_MASK;
time[2] |= WM8350_RTC_ALMMTH_MASK;
/* Set RTC_SET to stop the clock */
ret = wm8350_set_bits(wm8350, WM8350_RTC_TIME_CONTROL,
WM8350_RTC_ALMSET);
if (ret < 0)
return ret;
/* Wait until confirmation of stopping */
do {
rtc_ctrl = wm8350_reg_read(wm8350, WM8350_RTC_TIME_CONTROL);
schedule_timeout_interruptible(msecs_to_jiffies(1));
} while (retries-- && !(rtc_ctrl & WM8350_RTC_ALMSTS));
/* Write time to RTC */
ret = wm8350_block_write(wm8350, WM8350_ALARM_SECONDS_MINUTES,
3, time);
if (ret < 0)
return ret;
/* Clear RTC_ALMSET to enable the alarm */
ret = wm8350_clear_bits(wm8350, WM8350_RTC_TIME_CONTROL,
WM8350_RTC_ALMSET);
return ret;
}
static int wm8350_rtc_start_alarm(struct wm8350 *wm8350)
{
int ret;
int retries = WM8350_SET_ALM_RETRIES;
u16 rtc_ctrl;
ret = wm8350_clear_bits(wm8350, WM8350_RTC_TIME_CONTROL,
WM8350_RTC_ALMSET);
if (ret < 0)
return ret;
/* Wait until confirmation */
do {
rtc_ctrl = wm8350_reg_read(wm8350, WM8350_RTC_TIME_CONTROL);
schedule_timeout_uninterruptible(msecs_to_jiffies(1));
} while (retries-- && rtc_ctrl & WM8350_RTC_ALMSTS);
if (rtc_ctrl & WM8350_RTC_ALMSTS)
return -ETIMEDOUT;
return 0;
}
static int wm8350_rtc_stop_alarm(struct wm8350 *wm8350)
{
int retries = WM8350_SET_ALM_RETRIES;
u16 rtc_ctrl;
int ret;
/* Set RTC_SET to stop the clock */
ret = wm8350_set_bits(wm8350, WM8350_RTC_TIME_CONTROL,
WM8350_RTC_ALMSET);
if (ret < 0)
return ret;
/* Wait until confirmation of stopping */
do {
rtc_ctrl = wm8350_reg_read(wm8350, WM8350_RTC_TIME_CONTROL);
schedule_timeout_uninterruptible(msecs_to_jiffies(1));
} while (retries-- && !(rtc_ctrl & WM8350_RTC_ALMSTS));
if (!(rtc_ctrl & WM8350_RTC_ALMSTS))
return -ETIMEDOUT;
return 0;
}
static int wm8350_ldo_set_suspend_voltage(struct regulator_dev *rdev, int uV)
{
struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
int volt_reg, mV = uV / 1000, ldo = rdev_get_id(rdev);
u16 val;
dev_dbg(wm8350->dev, "%s %d mV %d\n", __func__, ldo, mV);
if (mV < 900 || mV > 3300) {
dev_err(wm8350->dev, "LDO%d voltage %d mV out of range\n",
ldo, mV);
return -EINVAL;
}
switch (ldo) {
case WM8350_LDO_1:
volt_reg = WM8350_LDO1_LOW_POWER;
break;
case WM8350_LDO_2:
volt_reg = WM8350_LDO2_LOW_POWER;
break;
case WM8350_LDO_3:
volt_reg = WM8350_LDO3_LOW_POWER;
break;
case WM8350_LDO_4:
volt_reg = WM8350_LDO4_LOW_POWER;
break;
default:
return -EINVAL;
}
/* all LDOs have same mV bits */
val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_VSEL_MASK;
wm8350_reg_write(wm8350, volt_reg,
val | wm8350_ldo_mvolts_to_val(mV));
return 0;
}
static int wm8350_dcdc_set_suspend_voltage(struct regulator_dev *rdev, int uV)
{
struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
int sel, volt_reg, dcdc = rdev_get_id(rdev);
u16 val;
dev_dbg(wm8350->dev, "%s %d mV %d\n", __func__, dcdc, uV / 1000);
switch (dcdc) {
case WM8350_DCDC_1:
volt_reg = WM8350_DCDC1_LOW_POWER;
break;
case WM8350_DCDC_3:
volt_reg = WM8350_DCDC3_LOW_POWER;
break;
case WM8350_DCDC_4:
volt_reg = WM8350_DCDC4_LOW_POWER;
break;
case WM8350_DCDC_6:
volt_reg = WM8350_DCDC6_LOW_POWER;
break;
case WM8350_DCDC_2:
case WM8350_DCDC_5:
default:
return -EINVAL;
}
sel = regulator_map_voltage_linear(rdev, uV, uV);
if (sel < 0)
return sel;
/* all DCDCs have same mV bits */
val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_DC1_VSEL_MASK;
wm8350_reg_write(wm8350, volt_reg, val | sel);
return 0;
}
static long wm8350_wdt_ioctl(struct file *file, unsigned int cmd,
unsigned long arg)
{
struct wm8350 *wm8350 = get_wm8350();
int ret = -ENOTTY, time, i;
void __user *argp = (void __user *)arg;
int __user *p = argp;
u16 reg;
switch (cmd) {
case WDIOC_GETSUPPORT:
ret = copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0;
break;
case WDIOC_GETSTATUS:
case WDIOC_GETBOOTSTATUS:
ret = put_user(0, p);
break;
case WDIOC_SETOPTIONS:
{
int options;
if (get_user(options, p))
return -EFAULT;
ret = -EINVAL;
/* Setting both simultaneously means at least one must fail */
if (options == WDIOS_DISABLECARD)
ret = wm8350_wdt_start(wm8350);
if (options == WDIOS_ENABLECARD)
ret = wm8350_wdt_stop(wm8350);
break;
}
case WDIOC_KEEPALIVE:
ret = wm8350_wdt_kick(wm8350);
break;
case WDIOC_SETTIMEOUT:
ret = get_user(time, p);
if (ret)
break;
if (time == 0) {
if (nowayout)
ret = -EINVAL;
else
wm8350_wdt_stop(wm8350);
break;
}
for (i = 0; i < ARRAY_SIZE(wm8350_wdt_cfgs); i++)
if (wm8350_wdt_cfgs[i].time == time)
break;
if (i == ARRAY_SIZE(wm8350_wdt_cfgs))
ret = -EINVAL;
else
ret = wm8350_wdt_set_timeout(wm8350,
wm8350_wdt_cfgs[i].val);
break;
case WDIOC_GETTIMEOUT:
reg = wm8350_reg_read(wm8350, WM8350_SYSTEM_CONTROL_2);
reg &= WM8350_WDOG_TO_MASK;
for (i = 0; i < ARRAY_SIZE(wm8350_wdt_cfgs); i++)
if (wm8350_wdt_cfgs[i].val == reg)
break;
if (i == ARRAY_SIZE(wm8350_wdt_cfgs)) {
dev_warn(wm8350->dev,
"Unknown watchdog configuration: %x\n", reg);
ret = -EINVAL;
} else
ret = put_user(wm8350_wdt_cfgs[i].time, p);
}
return ret;
}
//static int wm8350_init(struct wm8350 *wm8350)
int wm8350_dev_init(struct wm8350 *wm8350)
{
int i, ret;
u16 data;
#if 0
/* dont assert RTS when hibernating */
wm8350_set_bits(wm8350, WM8350_SYSTEM_HIBERNATE, WM8350_RST_HIB_MODE);
#endif
wm8350_reg_unlock(wm8350);
wm8350_set_bits(wm8350, WM8350_SYSTEM_CONTROL_1, WM8350_IRQ_POL);
wm8350_reg_lock(wm8350);
s3c2410_gpio_pullup(S3C2410_GPF1, 0);
s3c2410_gpio_cfgpin(S3C2410_GPF1, S3C2410_GPF1_EINT1);
// set_irq_type(IRQ_EINT1, IRQT_BOTHEDGE);
s3c2410_gpio_pullup(S3C2410_GPF2, 0);
s3c2410_gpio_cfgpin(S3C2410_GPF2, S3C2410_GPF2_EINT2);
/* Shutdown threshold value 3.1v off , 3.2v on */
wm8350_reg_unlock(wm8350);
data = wm8350_reg_read(wm8350, WM8350_POWER_CHECK_COMPARATOR)
& ~(WM8350_PCCMP_OFF_THR_MASK | WM8350_PCCMP_ON_THR_MASK);
wm8350_reg_write(wm8350, WM8350_POWER_CHECK_COMPARATOR, data | 0x23);
wm8350_reg_lock(wm8350);
data = wm8350_reg_read(wm8350, WM8350_DIGITISER_CONTROL_2);
wm8350_reg_write(wm8350, WM8350_DIGITISER_CONTROL_2, data | WM8350_AUXADC_CAL);
config_s3c_wm8350_gpio(wm8350);
#if 0
/* Sw1 --> PWR_ON */
wm8350_register_irq(wm8350, WM8350_IRQ_WKUP_ONKEY,
imx32ads_switch_handler, NULL);
wm8350_unmask_irq(wm8350, WM8350_IRQ_WKUP_ONKEY);
#endif
#ifndef CONFIG_MACH_CANOPUS
for (i = 0; i < ARRAY_SIZE(wm8350_regulator_devices); i++) {
platform_set_drvdata(&wm8350_regulator_devices[i], wm8350);
ret = platform_device_register(&wm8350_regulator_devices[i]);
if (ret < 0)
goto unwind;
}
#else // CONFIG_MACH_CANOPUS
struct regulator_init_data *reg_data = NULL;
for (i = 0; i < ARRAY_SIZE(wm8350_regulator_devices); i++) {
if (wm8350_regulator_devices[i].id == WM8350_DCDC_4) {
// for LCD
if (q_hw_ver(7800_ES2)
|| q_hw_ver(7800_TP)
|| q_hw_ver(7800_MP)) {
reg_data = (struct regulator_init_data *)wm8350_regulator_devices[i].dev.platform_data;
reg_data->constraints.min_uV = 3400000;
reg_data->constraints.max_uV = 3400000;
reg_data->constraints.state_mem.uV = 3400000;
}
} else if (wm8350_regulator_devices[i].id == WM8350_LDO_3) {
// for PMIC LDO
if (q_hw_ver(SWP2000)
|| q_hw_ver(7800_MP2)
|| q_hw_ver(KTQOOK_TP2)
|| q_hw_ver(KTQOOK_MP)
|| q_hw_ver(SKATM)) {
reg_data = (struct regulator_init_data *)wm8350_regulator_devices[i].dev.platform_data;
reg_data->constraints.min_uV = 1200000;
reg_data->constraints.max_uV = 1200000;
reg_data->num_consumer_supplies = ARRAY_SIZE(ldo4_consumers);
reg_data->consumer_supplies = ldo4_consumers;
}
} else if (wm8350_regulator_devices[i].id == WM8350_LDO_4) {
// for PMIC LDO
if (q_hw_ver(SWP2000)
|| q_hw_ver(7800_MP2)
|| q_hw_ver(KTQOOK_TP2)
|| q_hw_ver(KTQOOK_MP)
|| q_hw_ver(SKATM)) {
reg_data = (struct regulator_init_data *)wm8350_regulator_devices[i].dev.platform_data;
reg_data->constraints.min_uV = 3300000;
reg_data->constraints.max_uV = 3300000;
reg_data->num_consumer_supplies = ARRAY_SIZE(ldo3_consumers);
reg_data->consumer_supplies = ldo3_consumers;
}
}
platform_set_drvdata(&wm8350_regulator_devices[i], wm8350);
ret = platform_device_register(&wm8350_regulator_devices[i]);
if (ret < 0)
goto unwind;
}
#endif // CONFIG_MACH_CANOPUS
/* now register other clients */
return s3c_wm8350_device_register(wm8350);
unwind:
for (i--; i >= 0; i--)
platform_device_unregister(&wm8350_regulator_devices[i]);
return ret;
}
static int wm8350_rtc_probe(struct platform_device *pdev)
{
struct wm8350 *wm8350 = platform_get_drvdata(pdev);
struct wm8350_rtc *wm_rtc = &wm8350->rtc;
int ret = 0;
u16 timectl, power5;
timectl = wm8350_reg_read(wm8350, WM8350_RTC_TIME_CONTROL);
if (timectl & WM8350_RTC_BCD) {
dev_err(&pdev->dev, "RTC BCD mode not supported\n");
return -EINVAL;
}
if (timectl & WM8350_RTC_12HR) {
dev_err(&pdev->dev, "RTC 12 hour mode not supported\n");
return -EINVAL;
}
/* enable the RTC if it's not already enabled */
power5 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_5);
if (!(power5 & WM8350_RTC_TICK_ENA)) {
dev_info(wm8350->dev, "Starting RTC\n");
wm8350_reg_unlock(wm8350);
ret = wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5,
WM8350_RTC_TICK_ENA);
if (ret < 0) {
dev_err(&pdev->dev, "failed to enable RTC: %d\n", ret);
return ret;
}
wm8350_reg_lock(wm8350);
}
if (timectl & WM8350_RTC_STS) {
int retries;
ret = wm8350_clear_bits(wm8350, WM8350_RTC_TIME_CONTROL,
WM8350_RTC_SET);
if (ret < 0) {
dev_err(&pdev->dev, "failed to start: %d\n", ret);
return ret;
}
retries = WM8350_SET_TIME_RETRIES;
do {
timectl = wm8350_reg_read(wm8350,
WM8350_RTC_TIME_CONTROL);
} while (timectl & WM8350_RTC_STS && --retries);
if (retries == 0) {
dev_err(&pdev->dev, "failed to start: timeout\n");
return -ENODEV;
}
}
device_init_wakeup(&pdev->dev, 1);
wm_rtc->rtc = devm_rtc_device_register(&pdev->dev, "wm8350",
&wm8350_rtc_ops, THIS_MODULE);
if (IS_ERR(wm_rtc->rtc)) {
ret = PTR_ERR(wm_rtc->rtc);
dev_err(&pdev->dev, "failed to register RTC: %d\n", ret);
return ret;
}
wm8350_register_irq(wm8350, WM8350_IRQ_RTC_SEC,
wm8350_rtc_update_handler, 0,
"RTC Seconds", wm8350);
wm8350_mask_irq(wm8350, WM8350_IRQ_RTC_SEC);
wm8350_register_irq(wm8350, WM8350_IRQ_RTC_ALM,
wm8350_rtc_alarm_handler, 0,
"RTC Alarm", wm8350);
return 0;
}
