static void spiSetMode(uint8_t mode, uint8_t endian, uint8_t divider)
{
uint8_t cReg = 0;
/* set the mode */
if (mode & SPIMODE_CPOL)
cReg |= _BV(CPOL);
if (mode & SPIMODE_CPHA)
cReg |= _BV(CPHA);
/* set the endianness */
if (endian == SPIENDIAN_LITTLE)
cReg |= _BV(DORD);
/* set the divider */
if (divider & SPIDIV_SPR0)
cReg |= _BV(SPR0);
if (divider & SPIDIV_SPR1)
cReg |= _BV(SPR1);
/* write out to the registers */
writeIO(&SPCR, _BV(CPOL) | _BV(CPHA) | _BV(DORD) | _BV(SPR1) | _BV(SPR0),
cReg);
writeIO(&SPSR, _BV(SPI2X), (divider & SPIDIV_SPI2X) ? _BV(SPI2X) : 0);
}
void reset(){
io=io|CLR;
writeIO();
wait1Msec(10);
io=io & ~CLR;
writeIO();
}
/*
* Read the IO Port.
*
* Input:
* regType - Register Type
* ioIndex - When register type is OTHER_REGISTER, then ioIndex should
* contains the IO Port address. This will function just as
* regular IO port reading.
*/
unsigned char peekIO(
reg_type_t regType, /* Register Type */
unsigned short ioIndex /* IO Port Index */
)
{
unsigned char value;
switch (regType)
{
case MISCELLANEOUS_REGISTER:
value = readIO(0x3CC);
break;
case SEQUENCER_REGISTER:
writeIO(0x3C4, (unsigned char) ioIndex);
value = readIO(0x3C5);
break;
case CRT_REGISTER:
writeIO(0x3D4, (unsigned char) ioIndex);
value = readIO(0x3D5);
break;
case GRAPHICS_REGISTER:
writeIO(0x3CE, (unsigned char) ioIndex);
value = readIO(0x3CF);
break;
default:
value = readIO(ioIndex);
break;
}
return (value);
}
void calibrateGyro(){
drive(0);
io=io|calibrate;
writeIO();
wait1Msec(100);
io=io& ~calibrate;
writeIO();
wait1Msec(100);
}
/*
* Write to the IO Port.
*
* Input:
* regType - Register Type
* ioIndex - When register type is OTHER_REGISTER, then ioIndex should
* contains the IO Port address. This will function just as
* regular IO Port writing.
* value - The value to be written to the given register type and index.
*/
void pokeIO(
reg_type_t regType, /* Register Type */
unsigned short ioIndex, /* IO Port index */
unsigned char value /* Value to be written to the port */
)
{
switch (regType)
{
case MISCELLANEOUS_REGISTER:
writeIO(0x3C2, value);
break;
case SEQUENCER_REGISTER:
writeIO(0x3C4, (unsigned char) ioIndex);
writeIO(0x3C5, value);
break;
case CRT_REGISTER:
writeIO(0x3D4, (unsigned char) ioIndex);
writeIO(0x3D5, value);
break;
case GRAPHICS_REGISTER:
writeIO(0x3CE, (unsigned char) ioIndex);
writeIO(0x3CF, value);
break;
default:
writeIO(ioIndex, value);
break;
}
}
void rotateRightLP(ubyte amount, int pw){
setStrobe(HTPB,turnR | amount);
io=io|turning;
writeIO();
motor[left]=pw;
motor[right]=pw;
while(HTSPBreadADC(HTPB,almost,10)<600);
motor[left]=20;
motor[right]=20;
while(!HTSPBreadIO(HTPB,doneTurning));
drive(0);
io=io& ~turning;
io=io|doneTurning;
writeIO();
}
void SwitecX25::stepDown()
{
if (currentStep > 0) {
currentStep--;
currentState = (currentState + 5) % stateCount;
writeIO();
}
}
void SwitecX25::stepUp()
{
if (currentStep < steps) {
currentStep++;
currentState = (currentState + 1) % stateCount;
writeIO();
}
}
void writeCharToMem(int loc,char value) {
loc&=0xFFFF;
#if W_PRINTF == 1
printf("writeCharToMem loc: 0x%hhX value: 0x%hX\n",loc,value);
#endif
/*if(loc == 0xFFA6){
printf("writing %hhX to the value at PC: %hX\n",value,getPC());
}*/
if(loc<0xA000&&loc>=0x8000) { //VRam
vramBanks[(loc-0x8000)+0x2000*currentVramBank] = value;
} else if(loc<0xC000) { //Other Memcontroller stuff
//Call MEMcontroller Stuff
switch(mbcType) {
case 0:
// printf("Writing to MBC0! loc: %hX\n",loc);
break;
case 1:
// printf("Writing to MBC1! loc: %hX\n",loc);
memBankMBC1(loc,value);
break;
case 2:
// printf("Writing to MBC2! loc: %hX\n",loc);
memBankMBC2(loc,value);
break;
case 3:
// printf("Writing to MBC3! loc: %hX\n",loc);
memBankMBC3(loc,value);
break;
}
//memBankWrite(loc,value);
} else if(loc<0xD000) {
workBanks[(loc-0xC000)] = value;
} else if(loc<0xE000) {
workBanks[(loc-0xD000)+0x1000] = value;
} else if(loc<0xFE00) { //Same as 0xC000-0xDDFF
writeCharToMem(loc-0x2000,value);
} else if(loc<0xFEA0) { //OAM Table
OAMTable[(loc-0xFE00)] = value;
} else if(loc<0xFF00) { //Not Usable
//NOT USABLE
} else if(loc<0xFF80) { //I/O Ports
//IOPorts[(loc-0xFF00)] = value;
#if W_PRINTF == 1
printf("Calling writeIO\n");
#endif
writeIO(loc,value);
} else if(loc<0xFFFF) { //High RAM
//printf("Writing: 0x%hhX to 0x%X\n",value,loc);
hram[(loc-0xFF80)] = value;
} else { //Interrupt Enable Register
interruptER = value;
}
}
void spiInit(void)
{
#warning spi stuff is currently disabled
#if 0
/* set SS, SCLK and MOSI to output mode, and MISO to input mode */
writeIO(&DDR_SPI, SPI_ALL, SPI_ALL ^ SPI_MISO);
writeIO(&PORT_SPI, SPI_SS_NULL, SPI_SS_NULL);
/* ensure that all slave select pins are high */
spiUnselect();
/* disable power saving for SPI, and enable hardware SPI with interrupts
* disabled and master mode enabled */
writeIO(&PRR0, _BV(PRSPI), 0);
writeIO(&SPCR, _BV(SPE) | _BV(MSTR), _BV(SPE) | _BV(MSTR));
/* read the status and data registers to clear the state */
readIO(&SPSR, 0xff);
readIO(&SPDR, 0xff);
#endif
}
void intrInit(void)
{
/* set TIMER1 to run at F_CPU Hz and overflow when equal to OCR1A */
TCCR1B = _BV(CS10) | _BV(WGM12);
/* set the overflow threshold to 1/1000 second */
OCR1A = (F_CPU / 1000) - 1;
/* zero out the counter */
TCNT1 = 0;
/* enable interrupt when TCNT1 equals OCR1A */
writeIO(&TIMSK1, _BV(OCIE1A), _BV(OCIE1A));
/* enable interrupts */
sei();
}
void MMU::Write(const uint16_t location, const uint8_t value) {
// 0000 - 7fff => ROM (Not writable)
if (location < 0x8000) {
rom->controller->Write(location, value);
return;
}
// 8000 - 9fff => VRAM bank (switchable in GBC)
if (location < 0xa000) {
gpu->VRAM[gpu->VRAMbankId].bytes[location - 0x8000] = value;
return;
}
// a000 - bfff => External RAM (switchable)
if (location < 0xc000) {
rom->controller->Write(location, value);
return;
}
// c000 - cfff => Work RAM fixed bank
if (location < 0xd000) {
WRAM.bytes[location - 0xc000] = value;
return;
}
// d000 - dfff => Switchable Work RAM bank
if (location < 0xe000) {
WRAMbanks[WRAMbankId].bytes[location - 0xd000] = value;
return;
}
// e000 - fdff => Mirror of c000 - ddff (Not writable)
if (location < 0xfe00) { return; }
// fe00 - fe9f => Sprite attribute table
if (location < 0xfea0) {
// Get OAM item
uint8_t index = location / 4;
OAMBlock* block = &(gpu->sprites[index]);
// Get requested byte
uint8_t offset = location % 4;
switch (offset) {
case 0:
block->x = value;
return;
case 1:
block->y = value;
return;
case 2:
block->pattern = value;
return;
case 3:
block->flags.raw = value;
return;
default:
throw std::logic_error("Bad OAM offset");
}
}
// fea0 - feff => Not usable
if (location < 0xff00) { return; }
// ff00 - ff7f => I/O Registers
if (location < 0xff80) {
writeIO(location - 0xff00, value);
return;
}
// ff80 - fffe => High RAM (HRAM)
if (location < 0xffff) {
ZRAM.bytes[location - 0xff80] = value;
return;
}
// ffff => Interrupt mask
interruptEnable.raw = value;
}
