static void
tx4927_irq_cp0_modify(unsigned cp0_reg, unsigned clr_bits, unsigned set_bits)
{
unsigned long val = 0;
switch (cp0_reg) {
case CCP0_STATUS:
val = read_c0_status();
break;
case CCP0_CAUSE:
val = read_c0_cause();
break;
}
val &= (~clr_bits);
val |= (set_bits);
switch (cp0_reg) {
case CCP0_STATUS:{
write_c0_status(val);
break;
}
case CCP0_CAUSE:{
write_c0_cause(val);
break;
}
}
return;
}
static irqreturn_t brcm_reschedule_call_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
// we need to clear the interrupt...
register u32 temp;
temp = read_c0_cause();
temp &= ~CAUSEF_IP1;
write_c0_cause(temp);
return IRQ_HANDLED;
}
void mips_cpu_timer_enable(void)
{
uint32_t sr = read_c0_status();
sr |= ((0x1UL << 7) << 8);
write_c0_status(sr);
uint32_t cause = read_c0_cause();
cause &= ~(0x1UL << 27);
write_c0_cause(cause);
write_c0_compare(read_c0_count() + COUNTER_TICK_COUNT);
}
// Handle interprocessor messages
static irqreturn_t brcm_smp_call_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
/* SMP_CALL_FUNCTION */
smp_call_function_interrupt();
// we need to clear the interrupt...
{
register u32 temp;
temp = read_c0_cause();
temp &= ~CAUSEF_IP0;
write_c0_cause(temp);
}
return IRQ_HANDLED;
}
void core_send_ipi(int cpu, unsigned int action)
{
register unsigned long temp, value;
unsigned long flags;
local_irq_save (flags);
switch (action) {
case SMP_CALL_FUNCTION:
value = C_SW0;
break;
case SMP_RESCHEDULE_YOURSELF:
value = C_SW1;
break;
default:
return;
}
temp = read_c0_cause();
temp |= value;
write_c0_cause(temp);
local_irq_restore(flags);
}
