static void __init
ehci_orion_conf_mbus_windows(struct usb_hcd *hcd,
const struct mbus_dram_target_info *dram)
{
int i;
for (i = 0; i < 4; i++) {
wrl(USB_WINDOW_CTRL(i), 0);
wrl(USB_WINDOW_BASE(i), 0);
}
for (i = 0; i < dram->num_cs; i++) {
const struct mbus_dram_window *cs = dram->cs + i;
wrl(USB_WINDOW_CTRL(i), ((cs->size - 1) & 0xffff0000) |
(cs->mbus_attr << 8) |
(dram->mbus_dram_target_id << 4) | 1);
wrl(USB_WINDOW_BASE(i), cs->base);
}
}
/*
* USB 2.0 Bridge Address Decoding registers setup
*/
static void usb_brg_adrdec_setup(void)
{
int i;
u32 size, base, attrib;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
/* Enable DRAM bank */
switch (i) {
case 0:
attrib = MVUSB0_CPU_ATTR_DRAM_CS0;
break;
case 1:
attrib = MVUSB0_CPU_ATTR_DRAM_CS1;
break;
case 2:
attrib = MVUSB0_CPU_ATTR_DRAM_CS2;
break;
case 3:
attrib = MVUSB0_CPU_ATTR_DRAM_CS3;
break;
default:
/* invalide bank, disable access */
attrib = 0;
break;
}
size = gd->bd->bi_dram[i].size;
base = gd->bd->bi_dram[i].start;
if ((size) && (attrib))
wrl(USB_WINDOW_CTRL(i),
MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
attrib, MVCPU_WIN_ENABLE));
else
wrl(USB_WINDOW_CTRL(i), MVCPU_WIN_DISABLE);
wrl(USB_WINDOW_BASE(i), base);
}
}
/*
* Implement Orion USB controller specification guidelines
*/
static void orion_usb_phy_v1_setup(struct usb_hcd *hcd)
{
/* The below GLs are according to the Orion Errata document */
/*
* Clear interrupt cause and mask
*/
wrl(USB_CAUSE, 0);
wrl(USB_MASK, 0);
/*
* Reset controller
*/
wrl(USB_CMD, rdl(USB_CMD) | 0x2);
while (rdl(USB_CMD) & 0x2);
/*
* GL# USB-10: Set IPG for non start of frame packets
* Bits[14:8]=0xc
*/
wrl(USB_IPG, (rdl(USB_IPG) & ~0x7f00) | 0xc00);
/*
* GL# USB-9: USB 2.0 Power Control
* BG_VSEL[7:6]=0x1
*/
wrl(USB_PHY_PWR_CTRL, (rdl(USB_PHY_PWR_CTRL) & ~0xc0)| 0x40);
/*
* GL# USB-1: USB PHY Tx Control - force calibration to '8'
* TXDATA_BLOCK_EN[21]=0x1, EXT_RCAL_EN[13]=0x1, IMP_CAL[6:3]=0x8
*/
wrl(USB_PHY_TX_CTRL, (rdl(USB_PHY_TX_CTRL) & ~0x78) | 0x202040);
/*
* GL# USB-3 GL# USB-9: USB PHY Rx Control
* RXDATA_BLOCK_LENGHT[31:30]=0x3, EDGE_DET_SEL[27:26]=0,
* CDR_FASTLOCK_EN[21]=0, DISCON_THRESHOLD[9:8]=0, SQ_THRESH[7:4]=0x1
*/
wrl(USB_PHY_RX_CTRL, (rdl(USB_PHY_RX_CTRL) & ~0xc2003f0) | 0xc0000010);
/*
* GL# USB-3 GL# USB-9: USB PHY IVREF Control
* PLLVDD12[1:0]=0x2, RXVDD[5:4]=0x3, Reserved[19]=0
*/
wrl(USB_PHY_IVREF_CTRL, (rdl(USB_PHY_IVREF_CTRL) & ~0x80003 ) | 0x32);
/*
* GL# USB-3 GL# USB-9: USB PHY Test Group Control
* REG_FIFO_SQ_RST[15]=0
*/
wrl(USB_PHY_TST_GRP_CTRL, rdl(USB_PHY_TST_GRP_CTRL) & ~0x8000);
/*
* Stop and reset controller
*/
wrl(USB_CMD, rdl(USB_CMD) & ~0x1);
wrl(USB_CMD, rdl(USB_CMD) | 0x2);
while (rdl(USB_CMD) & 0x2);
/*
* GL# USB-5 Streaming disable REG_USB_MODE[4]=1
* TBD: This need to be done after each reset!
* GL# USB-4 Setup USB Host mode
*/
wrl(USB_MODE, 0x13);
}
static int
ds_init(struct sc_info *sc)
{
int i;
u_int32_t *ci, r, pcs, rcs, ecs, ws, memsz, cb;
u_int8_t *t;
void *buf;
ci = ds_devs[sc->type].mcode;
ds_wr(sc, YDSXGR_NATIVEDACOUTVOL, 0x00000000, 4);
ds_enadsp(sc, 0);
ds_wr(sc, YDSXGR_MODE, 0x00010000, 4);
ds_wr(sc, YDSXGR_MODE, 0x00000000, 4);
ds_wr(sc, YDSXGR_MAPOFREC, 0x00000000, 4);
ds_wr(sc, YDSXGR_MAPOFEFFECT, 0x00000000, 4);
ds_wr(sc, YDSXGR_PLAYCTRLBASE, 0x00000000, 4);
ds_wr(sc, YDSXGR_RECCTRLBASE, 0x00000000, 4);
ds_wr(sc, YDSXGR_EFFCTRLBASE, 0x00000000, 4);
r = ds_rd(sc, YDSXGR_GLOBALCTRL, 2);
ds_wr(sc, YDSXGR_GLOBALCTRL, r & ~0x0007, 2);
for (i = 0; i < YDSXG_DSPLENGTH; i += 4)
ds_wr(sc, YDSXGR_DSPINSTRAM + i, DspInst[i >> 2], 4);
for (i = 0; i < YDSXG_CTRLLENGTH; i += 4)
ds_wr(sc, YDSXGR_CTRLINSTRAM + i, ci[i >> 2], 4);
ds_enadsp(sc, 1);
pcs = 0;
for (i = 100; i > 0; i--) {
pcs = ds_rd(sc, YDSXGR_PLAYCTRLSIZE, 4) << 2;
if (pcs == sizeof(struct pbank))
break;
DELAY(1000);
}
if (pcs != sizeof(struct pbank)) {
device_printf(sc->dev, "preposterous playctrlsize (%d)\n", pcs);
return -1;
}
rcs = ds_rd(sc, YDSXGR_RECCTRLSIZE, 4) << 2;
ecs = ds_rd(sc, YDSXGR_EFFCTRLSIZE, 4) << 2;
ws = ds_rd(sc, YDSXGR_WORKSIZE, 4) << 2;
memsz = 64 * 2 * pcs + 2 * 2 * rcs + 5 * 2 * ecs + ws;
memsz += (64 + 1) * 4;
if (sc->regbase == NULL) {
if (bus_dma_tag_create(bus_get_dma_tag(sc->dev), 2, 0,
BUS_SPACE_MAXADDR_32BIT,
BUS_SPACE_MAXADDR,
NULL, NULL, memsz, 1, memsz, 0, NULL,
NULL, &sc->control_dmat))
return -1;
if (bus_dmamem_alloc(sc->control_dmat, &buf, BUS_DMA_NOWAIT, &sc->map))
return -1;
if (bus_dmamap_load(sc->control_dmat, sc->map, buf, memsz, ds_setmap, sc, 0) || !sc->ctrlbase) {
device_printf(sc->dev, "pcs=%d, rcs=%d, ecs=%d, ws=%d, memsz=%d\n",
pcs, rcs, ecs, ws, memsz);
return -1;
}
sc->regbase = buf;
} else
buf = sc->regbase;
cb = 0;
t = buf;
ds_wr(sc, YDSXGR_WORKBASE, sc->ctrlbase + cb, 4);
cb += ws;
sc->pbase = (u_int32_t *)(t + cb);
/* printf("pbase = %p -> 0x%x\n", sc->pbase, sc->ctrlbase + cb); */
ds_wr(sc, YDSXGR_PLAYCTRLBASE, sc->ctrlbase + cb, 4);
cb += (64 + 1) * 4;
sc->rbank = (struct rbank *)(t + cb);
ds_wr(sc, YDSXGR_RECCTRLBASE, sc->ctrlbase + cb, 4);
cb += 2 * 2 * rcs;
ds_wr(sc, YDSXGR_EFFCTRLBASE, sc->ctrlbase + cb, 4);
cb += 5 * 2 * ecs;
sc->pbankbase = sc->ctrlbase + cb;
sc->pbanksize = pcs;
for (i = 0; i < 64; i++) {
wrl(sc, &sc->pbase[i + 1], 0);
sc->pbank[i * 2] = (struct pbank *)(t + cb);
/* printf("pbank[%d] = %p -> 0x%x; ", i * 2, (struct pbank *)(t + cb), sc->ctrlbase + cb - vtophys(t + cb)); */
cb += pcs;
sc->pbank[i * 2 + 1] = (struct pbank *)(t + cb);
/* printf("pbank[%d] = %p -> 0x%x\n", i * 2 + 1, (struct pbank *)(t + cb), sc->ctrlbase + cb - vtophys(t + cb)); */
cb += pcs;
}
wrl(sc, &sc->pbase[0], DS1_CHANS * 2);
sc->pchn = sc->rchn = 0;
ds_wr(sc, YDSXGR_NATIVEDACOUTVOL, 0x3fff3fff, 4);
ds_wr(sc, YDSXGR_NATIVEADCINVOL, 0x3fff3fff, 4);
ds_wr(sc, YDSXGR_NATIVEDACINVOL, 0x3fff3fff, 4);
return 0;
}
static void
ds_enapslot(struct sc_info *sc, int slot, int go)
{
wrl(sc, &sc->pbase[slot + 1], go? (sc->pbankbase + 2 * slot * sc->pbanksize) : 0);
/* printf("pbase[%d] = 0x%x\n", slot + 1, go? (sc->pbankbase + 2 * slot * sc->pbanksize) : 0); */
}
static void orion_usb_phy_v2_setup(struct usb_hcd *hcd)
{
u32 reg;
/* The below GLs are according to the Orion Errata document */
/*
* Clear interrupt cause and mask
*/
wrl(USB_CAUSE, 0);
wrl(USB_MASK, 0);
/*
* Reset controller
*/
wrl(USB_CMD, rdl(USB_CMD) | 0x2);
while (rdl(USB_CMD) & 0x2);
/* Clear bits 30 and 31.
*/
reg = rdl(USB_IPG);
reg &= ~(0x3 << 30);
/* Change bits[14:8] - IPG for non Start of Frame Packets
* from 0x9(default) to 0xD
*/
reg &= ~(0x7f << 8);
reg |= 0xd << 8;
wrl(USB_IPG, reg);
/* VCO recalibrate */
wrl(USB_PHY_PLL_CTRL, rdl(USB_PHY_PLL_CTRL) | (1 << 21));
udelay(100);
wrl(USB_PHY_PLL_CTRL, rdl(USB_PHY_PLL_CTRL) & ~(1 << 21));
reg = rdl(USB_PHY_TX_CTRL);
reg |= 1 << 11; /* LOWVDD_EN */
reg |= 1 << 12; /* REG_RCAL_START */
/* bits[16:14] (IMPCAL_VTH[2:0] = 101) */
reg &= ~(0x7 << 14);
reg |= (0x5 << 14);
reg &= ~(1 << 21); /* TX_BLOCK_EN */
reg &= ~(1 << 31); /* HS_STRESS_CTRL */
wrl(USB_PHY_TX_CTRL, reg);
udelay(100);
reg = rdl(USB_PHY_TX_CTRL);
reg &= ~(1 << 12); /* REG_RCAL_START */
wrl(USB_PHY_TX_CTRL, reg);
reg = rdl(USB_PHY_RX_CTRL);
reg &= ~(3 << 2); /* LPL_COEF */
reg |= 1 << 2;
reg &= ~(0xf << 4);
reg |= 0xc << 4; /* SQ_THRESH */
reg &= ~(3 << 15); /* REG_SQ_LENGTH */
reg |= 1 << 15;
reg &= ~(1 << 21); /* CDR_FASTLOCK_EN */
reg &= ~(3 << 26); /* EDGE_DET */
wrl(USB_PHY_RX_CTRL, reg);
/*
* USB PHY IVREF Control
* TXVDD12[9:8]=0x3
*/
wrl(USB_PHY_IVREF_CTRL, rdl(USB_PHY_IVREF_CTRL) | (0x3 << 8));
/*
* GL# USB-3 GL# USB-9: USB PHY Test Group Control
* REG_FIFO_SQ_RST[15]=0
*/
wrl(USB_PHY_TST_GRP_CTRL, rdl(USB_PHY_TST_GRP_CTRL) & ~0x8000);
/*
* Stop and reset controller
*/
wrl(USB_CMD, rdl(USB_CMD) & ~0x1);
wrl(USB_CMD, rdl(USB_CMD) | 0x2);
while (rdl(USB_CMD) & 0x2);
/*
* GL# USB-4 Setup USB Host mode
*/
wrl(USB_MODE, 0x3);
}
static void orion_usb_phy_v1_setup(struct usb_hcd *hcd)
{
wrl(USB_CAUSE, 0);
wrl(USB_MASK, 0);
wrl(USB_CMD, rdl(USB_CMD) | 0x2);
while (rdl(USB_CMD) & 0x2);
wrl(USB_IPG, (rdl(USB_IPG) & ~0x7f00) | 0xc00);
wrl(USB_PHY_PWR_CTRL, (rdl(USB_PHY_PWR_CTRL) & ~0xc0)| 0x40);
wrl(USB_PHY_TX_CTRL, (rdl(USB_PHY_TX_CTRL) & ~0x78) | 0x202040);
wrl(USB_PHY_RX_CTRL, (rdl(USB_PHY_RX_CTRL) & ~0xc2003f0) | 0xc0000010);
wrl(USB_PHY_IVREF_CTRL, (rdl(USB_PHY_IVREF_CTRL) & ~0x80003 ) | 0x32);
wrl(USB_PHY_TST_GRP_CTRL, rdl(USB_PHY_TST_GRP_CTRL) & ~0x8000);
wrl(USB_CMD, rdl(USB_CMD) & ~0x1);
wrl(USB_CMD, rdl(USB_CMD) | 0x2);
while (rdl(USB_CMD) & 0x2);
wrl(USB_MODE, 0x13);
}