/* Disables as many prefetchers as possible */
BOOT_CODE bool_t
disablePrefetchers()
{
x86_cpu_identity_t *model_info;
uint32_t low, high;
word_t i;
uint32_t valid_models[] = { BROADWELL_1_MODEL_ID, BROADWELL_2_MODEL_ID,
BROADWELL_3_MODEL_ID, BROADWELL_4_MODEL_ID,
BROADWELL_5_MODEL_ID,
HASWELL_1_MODEL_ID, HASWELL_2_MODEL_ID,
HASWELL_3_MODEL_ID, HASWELL_4_MODEL_ID,
IVY_BRIDGE_1_MODEL_ID, IVY_BRIDGE_2_MODEL_ID,
IVY_BRIDGE_3_MODEL_ID,
SANDY_BRIDGE_1_MODEL_ID, SANDY_BRIDGE_2_MODEL_ID, WESTMERE_1_MODEL_ID, WESTMERE_2_MODEL_ID,
WESTMERE_3_MODEL_ID, NEHALEM_1_MODEL_ID, NEHALEM_2_MODEL_ID, NEHALEM_3_MODEL_ID
};
model_info = x86_cpuid_get_model_info();
for (i = 0; i < ARRAY_SIZE(valid_models); i++) {
/* The model ID is only useful when hashed together with the family ID.
* They are both meant to be combined to form a unique identifier.
*
* As far as I can tell though, we might be able to actually just
* disable prefetching on anything that matches family_ID==0x6, and
* there is no need to also look at the model_ID.
*/
if (model_info->family == IA32_PREFETCHER_COMPATIBLE_FAMILIES_ID
&& model_info->model == valid_models[i]) {
low = x86_rdmsr_low(IA32_PREFETCHER_MSR);
high = x86_rdmsr_high(IA32_PREFETCHER_MSR);
low |= IA32_PREFETCHER_MSR_L2;
low |= IA32_PREFETCHER_MSR_L2_ADJACENT;
low |= IA32_PREFETCHER_MSR_DCU;
low |= IA32_PREFETCHER_MSR_DCU_IP;
x86_wrmsr(IA32_PREFETCHER_MSR, ((uint64_t)high) << 32 | low);
return true;
}
}
printf("Disabling prefetchers not implemented for CPU fam %x model %x\n",
model_info->family, model_info->model);
return false;
}
BOOT_CODE bool_t Arch_initHardwareBreakpoints(void)
{
x86_cpu_identity_t *modelinfo;
modelinfo = x86_cpuid_get_model_info();
/* Intel manuals, vol3, section 17.2.4, "NOTES". */
if (modelinfo->family == 15) {
if (modelinfo->model == 3 || modelinfo->model == 4
|| modelinfo->model == 6) {
byte8_bps_supported = true;
}
}
if (modelinfo->family == 6) {
if (modelinfo->model == 15 || modelinfo->model == 23
|| modelinfo->model == 0x1C) {
byte8_bps_supported = true;
}
}
return true;
}
static BOOT_CODE bool_t
is_compiled_for_microarchitecture(void)
{
word_t microarch_generation = 0;
x86_cpu_identity_t *model_info = x86_cpuid_get_model_info();
if (config_set(CONFIG_ARCH_X86_SKYLAKE) ) {
microarch_generation = 7;
} else if (config_set(CONFIG_ARCH_X86_BROADWELL) ) {
microarch_generation = 6;
} else if (config_set(CONFIG_ARCH_X86_HASWELL) ) {
microarch_generation = 5;
} else if (config_set(CONFIG_ARCH_X86_IVY) ) {
microarch_generation = 4;
} else if (config_set(CONFIG_ARCH_X86_SANDY) ) {
microarch_generation = 3;
} else if (config_set(CONFIG_ARCH_X86_WESTMERE) ) {
microarch_generation = 2;
} else if (config_set(CONFIG_ARCH_X86_NEHALEM) ) {
microarch_generation = 1;
}
switch (model_info->model) {
case SKYLAKE_1_MODEL_ID:
case SKYLAKE_2_MODEL_ID:
if (microarch_generation > 7) {
return false;
}
break;
case BROADWELL_1_MODEL_ID:
case BROADWELL_2_MODEL_ID:
case BROADWELL_3_MODEL_ID:
case BROADWELL_4_MODEL_ID:
case BROADWELL_5_MODEL_ID:
if (microarch_generation > 6) {
return false;
}
break;
case HASWELL_1_MODEL_ID:
case HASWELL_2_MODEL_ID:
case HASWELL_3_MODEL_ID:
case HASWELL_4_MODEL_ID:
if (microarch_generation > 5) {
return false;
}
break;
case IVY_BRIDGE_1_MODEL_ID:
case IVY_BRIDGE_2_MODEL_ID:
case IVY_BRIDGE_3_MODEL_ID:
if (microarch_generation > 4) {
return false;
}
break;
case SANDY_BRIDGE_1_MODEL_ID:
case SANDY_BRIDGE_2_MODEL_ID:
if (microarch_generation > 3) {
return false;
}
break;
case WESTMERE_1_MODEL_ID:
case WESTMERE_2_MODEL_ID:
case WESTMERE_3_MODEL_ID:
if (microarch_generation > 2) {
return false;
}
break;
case NEHALEM_1_MODEL_ID:
case NEHALEM_2_MODEL_ID:
case NEHALEM_3_MODEL_ID:
if (microarch_generation > 1) {
return false;
}
break;
default:
if (!config_set(CONFIG_ARCH_X86_GENERIC)) {
return false;
}
}
return true;
}
