/**
* zynq_slcr_init_postload_fpga - Re-enable communication from the PL to PS.
*/
void zynq_slcr_init_postload_fpga(void)
{
/* Enable level shifters */
zynq_slcr_write(0xf, SLCR_LVL_SHFTR_EN_OFFSET);
/* Deassert AXI interface resets */
zynq_slcr_write(0, SLCR_FPGA_RST_CTRL_OFFSET);
}
/**
* zynq_slcr_cpu_start - Start cpu
* @cpu: cpu number
*/
void zynq_slcr_cpu_start(int cpu)
{
u32 reg;
zynq_slcr_read(®, SLCR_A9_CPU_RST_CTRL_OFFSET);
reg &= ~(SLCR_A9_CPU_RST << cpu);
zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu);
zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
}
/**
* zynq_slcr_init_preload_fpga - Disable communication from the PL to PS.
*/
void zynq_slcr_init_preload_fpga(void)
{
/* Assert FPGA top level output resets */
zynq_slcr_write(0xF, SLCR_FPGA_RST_CTRL_OFFSET);
/* Disable level shifters */
zynq_slcr_write(0, SLCR_LVL_SHFTR_EN_OFFSET);
/* Enable output level shifters */
zynq_slcr_write(0xA, SLCR_LVL_SHFTR_EN_OFFSET);
}
static void zynq_cpu_start(cyg_uint32 cpu) {
cyg_uint32 reg;
zynq_slcr_unlock();
reg = zynq_slcr_read(XSLCR_A9_CPU_RST_CTRL_OFFSET);
reg &= ~(XSLCR_A9_CPU_RST << cpu);
zynq_slcr_write(XSLCR_A9_CPU_RST_CTRL_OFFSET, reg);
reg &= ~(XSLCR_A9_CPU_STOP << cpu);
zynq_slcr_write(XSLCR_A9_CPU_RST_CTRL_OFFSET, reg);
zynq_slcr_lock();
}
/**
* zynq_slcr_system_restart - Restart the entire system.
*
* @nb: Pointer to restart notifier block (unused)
* @action: Reboot mode (unused)
* @data: Restart handler private data (unused)
*
* Return: 0 always
*/
static
int zynq_slcr_system_restart(struct notifier_block *nb,
unsigned long action, void *data)
{
u32 reboot;
/*
* Clear 0x0F000000 bits of reboot status register to workaround
* the FSBL not loading the bitstream after soft-reboot
* This is a temporary solution until we know more.
*/
zynq_slcr_read(&reboot, SLCR_REBOOT_STATUS_OFFSET);
zynq_slcr_write(reboot & 0xF0FFFFFF, SLCR_REBOOT_STATUS_OFFSET);
zynq_slcr_write(1, SLCR_PS_RST_CTRL_OFFSET);
return 0;
}
/**
* zynq_slcr_cpu_stop - Stop cpu
* @cpu: cpu number
*/
void zynq_slcr_cpu_stop(int cpu)
{
u32 reg;
zynq_slcr_read(®, SLCR_A9_CPU_RST_CTRL_OFFSET);
reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu;
zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
}
/**
* zynq_slcr_system_reset - Reset the entire system.
*/
void zynq_slcr_system_reset(void)
{
u32 reboot;
/*
* Unlock the SLCR then reset the system.
* Note that this seems to require raw i/o
* functions or there's a lockup?
*/
zynq_slcr_unlock();
/*
* Clear 0x0F000000 bits of reboot status register to workaround
* the FSBL not loading the bitstream after soft-reboot
* This is a temporary solution until we know more.
*/
zynq_slcr_read(&reboot, SLCR_REBOOT_STATUS_OFFSET);
zynq_slcr_write(reboot & 0xF0FFFFFF, SLCR_REBOOT_STATUS_OFFSET);
zynq_slcr_write(1, SLCR_PS_RST_CTRL_OFFSET);
}
void zynq_cpu_stop(cyg_uint32 cpu) {
cyg_uint32 reg;
zynq_slcr_unlock();
reg = zynq_slcr_read(XSLCR_A9_CPU_RST_CTRL_OFFSET);
reg |= (XSLCR_A9_CPU_STOP | XSLCR_A9_CPU_RST) << cpu;
zynq_slcr_write(XSLCR_A9_CPU_RST_CTRL_OFFSET, reg);
zynq_slcr_lock();
}
/**
* zynq_slcr_unlock - Unlock SLCR registers
*
* Return: a negative value on error, 0 on success
*/
static inline int zynq_slcr_unlock(void)
{
zynq_slcr_write(SLCR_UNLOCK_MAGIC, SLCR_UNLOCK_OFFSET);
return 0;
}
