/**
* xpsgtr_set_sgmii_pcs - This function sets the sgmii mode for GEM.
* @gtr_phy: pointer to lane
*
* Return: 0 on success, -EINVAL on non existing SGMII type or error from
* communication with firmware
*/
static int xpsgtr_set_sgmii_pcs(struct xpsgtr_phy *gtr_phy)
{
u32 shift, mask, value;
u32 ret = 0;
struct xpsgtr_dev *gtr_dev = gtr_phy->data;
/* Set the PCS signal detect to 1 */
switch (gtr_phy->type) {
case XPSGTR_TYPE_SGMII0:
shift = 0;
break;
case XPSGTR_TYPE_SGMII1:
shift = 1;
break;
case XPSGTR_TYPE_SGMII2:
shift = 2;
break;
case XPSGTR_TYPE_SGMII3:
shift = 3;
break;
default:
return -EINVAL;
}
/* Tie the GEM PCS Signal Detect to 1 */
mask = SGMII_SD_MASK << SGMII_SD_OFFSET * shift;
value = SGMII_PCS_SD_1 << SGMII_SD_OFFSET * shift;
ret = zynqmp_pm_mmio_write(IOU_SLCR + IOU_GEM_CTRL_OFFSET, mask, value);
if (ret < 0) {
dev_err(gtr_dev->dev, "failed to set GEM PCS SD\n");
return ret;
}
/* Set the GEM to SGMII mode */
mask = GEM_CLK_CTRL_MASK << GEM_CLK_CTRL_OFFSET * shift;
value = GEM_RX_SRC_SEL_GTR | GEM_SGMII_MODE;
ret = zynqmp_pm_mmio_write(IOU_SLCR + IOU_GEM_CLK_CTRL_OFFSET,
mask, value);
if (ret < 0) {
dev_err(gtr_dev->dev, "failed to set GEM to SGMII mode\n");
return ret;
}
return ret;
}
/**
* zynqmp_pll_disable - Disable clock
* @hw: Handle between common and hardware-specific interfaces
*
*/
static void zynqmp_pll_disable(struct clk_hw *hw)
{
struct zynqmp_pll *clk = to_zynqmp_pll(hw);
if (!zynqmp_pll_is_enabled(hw))
return;
pr_info("PLL: shutdown\n");
/* shut down PLL */
zynqmp_pm_mmio_write((u32)(ulong)clk->pll_ctrl, PLLCTRL_RESET_MASK,
PLLCTRL_RESET_VAL);
}
/**
* pll_frac_set_mode - Set the fractional mode
* @hw: Handle between common and hardware-specific interfaces
* @on: Flag to determine the mode
*/
static inline void pll_frac_set_mode(struct clk_hw *hw, bool on)
{
struct zynqmp_pll *clk = to_zynqmp_pll(hw);
u32 reg = 0;
int ret;
if (on)
reg = PLLFCFG_FRAC_EN;
ret = zynqmp_pm_mmio_write((u32)(ulong)(clk->pll_ctrl + FRAC_OFFSET),
PLLFCFG_FRAC_EN, reg);
if (ret)
pr_warn_once("Write fail pll address: %x\n",
(u32)(ulong)(clk->pll_ctrl + FRAC_OFFSET));
}
