static void gic_pre_save(void *opaque)
{
GICState *s = (GICState *)opaque;
ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s);
if (c->pre_save) {
c->pre_save(s);
}
}
static int gic_post_load(void *opaque, int version_id)
{
GICState *s = (GICState *)opaque;
ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s);
if (c->post_load) {
c->post_load(s);
}
return 0;
}
static int gic_load(QEMUFile *f, void *opaque, int version_id)
{
gic_state *s = (gic_state *)opaque;
ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s);
int i;
int j;
if (version_id != 3) {
return -EINVAL;
}
s->enabled = qemu_get_be32(f);
for (i = 0; i < s->num_cpu; i++) {
s->cpu_enabled[i] = qemu_get_be32(f);
for (j = 0; j < GIC_INTERNAL; j++) {
s->priority1[j][i] = qemu_get_be32(f);
}
for (j = 0; j < s->num_irq; j++) {
s->last_active[j][i] = qemu_get_be32(f);
}
s->priority_mask[i] = qemu_get_be32(f);
s->running_irq[i] = qemu_get_be32(f);
s->running_priority[i] = qemu_get_be32(f);
s->current_pending[i] = qemu_get_be32(f);
}
for (i = 0; i < s->num_irq - GIC_INTERNAL; i++) {
s->priority2[i] = qemu_get_be32(f);
}
for (i = 0; i < s->num_irq; i++) {
s->irq_target[i] = qemu_get_be32(f);
s->irq_state[i].enabled = qemu_get_byte(f);
s->irq_state[i].pending = qemu_get_byte(f);
s->irq_state[i].active = qemu_get_byte(f);
s->irq_state[i].level = qemu_get_byte(f);
s->irq_state[i].model = qemu_get_byte(f);
s->irq_state[i].trigger = qemu_get_byte(f);
}
if (c->post_load) {
c->post_load(s);
}
return 0;
}
static void gic_save(QEMUFile *f, void *opaque)
{
gic_state *s = (gic_state *)opaque;
ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s);
int i;
int j;
if (c->pre_save) {
c->pre_save(s);
}
qemu_put_be32(f, s->enabled);
for (i = 0; i < s->num_cpu; i++) {
qemu_put_be32(f, s->cpu_enabled[i]);
for (j = 0; j < GIC_INTERNAL; j++) {
qemu_put_be32(f, s->priority1[j][i]);
}
for (j = 0; j < s->num_irq; j++) {
qemu_put_be32(f, s->last_active[j][i]);
}
qemu_put_be32(f, s->priority_mask[i]);
qemu_put_be32(f, s->running_irq[i]);
qemu_put_be32(f, s->running_priority[i]);
qemu_put_be32(f, s->current_pending[i]);
}
for (i = 0; i < s->num_irq - GIC_INTERNAL; i++) {
qemu_put_be32(f, s->priority2[i]);
}
for (i = 0; i < s->num_irq; i++) {
qemu_put_be32(f, s->irq_target[i]);
qemu_put_byte(f, s->irq_state[i].enabled);
qemu_put_byte(f, s->irq_state[i].pending);
qemu_put_byte(f, s->irq_state[i].active);
qemu_put_byte(f, s->irq_state[i].level);
qemu_put_byte(f, s->irq_state[i].model);
qemu_put_byte(f, s->irq_state[i].trigger);
}
}
