C++ (Cpp) RegClassVector Beispiele

Beispiel #1

bool PPCSubtarget::enablePostRAScheduler(
           CodeGenOpt::Level OptLevel,
           TargetSubtargetInfo::AntiDepBreakMode& Mode,
           RegClassVector& CriticalPathRCs) const {
  // FIXME: It would be best to use TargetSubtargetInfo::ANTIDEP_ALL here,
  // but we can't because we can't reassign the cr registers. There is a
  // dependence between the cr register and the RLWINM instruction used
  // to extract its value which the anti-dependency breaker can't currently
  // see. Maybe we should make a late-expanded pseudo to encode this dependency.
  // (the relevant code is in PPCDAGToDAGISel::SelectSETCC)

  Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;

  CriticalPathRCs.clear();

  if (isPPC64())
    CriticalPathRCs.push_back(&PPC::G8RCRegClass);
  else
    CriticalPathRCs.push_back(&PPC::GPRCRegClass);
    
  CriticalPathRCs.push_back(&PPC::F8RCRegClass);
  CriticalPathRCs.push_back(&PPC::VRRCRegClass);

  return OptLevel >= CodeGenOpt::Default;
}

Beispiel #2

Datei: ARMSubtarget.cpp Projekt: JiaHung/Git_function_prac

bool ARMSubtarget::enablePostRAScheduler(
           CodeGenOpt::Level OptLevel,
           TargetSubtargetInfo::AntiDepBreakMode& Mode,
           RegClassVector& CriticalPathRCs) const {
  Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
  CriticalPathRCs.clear();
  CriticalPathRCs.push_back(&ARM::GPRRegClass);
  return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
}

Beispiel #3

Datei: CoffeeSubtarget.cpp Projekt: guoqingzhang/llvm-coffee

bool
CoffeeSubtarget::enablePostRAScheduler(CodeGenOpt::Level OptLevel,
                                    TargetSubtargetInfo::AntiDepBreakMode &Mode,
                                     RegClassVector &CriticalPathRCs) const {
  Mode = TargetSubtargetInfo::ANTIDEP_NONE;
  CriticalPathRCs.clear();
  CriticalPathRCs.push_back(&Coffee::GPRCRegClass);
  return OptLevel >= CodeGenOpt::Aggressive;
}

Beispiel #4

Datei: MipsSubtarget.cpp Projekt: apiotrow/emscripten-fastcomp

bool
MipsSubtarget::enablePostRAScheduler(CodeGenOpt::Level OptLevel,
                                    TargetSubtargetInfo::AntiDepBreakMode &Mode,
                                     RegClassVector &CriticalPathRCs) const {
  Mode = TargetSubtargetInfo::ANTIDEP_NONE;
  CriticalPathRCs.clear();
  CriticalPathRCs.push_back(hasMips64() ?
                            &Mips::GPR64RegClass : &Mips::GPR32RegClass);
  return OptLevel >= CodeGenOpt::Aggressive;
}

Beispiel #5

Datei: PPCSubtarget.cpp Projekt: ADonut/LLVM-GPGPU

bool PPCSubtarget::enablePostRAScheduler(
           CodeGenOpt::Level OptLevel,
           TargetSubtargetInfo::AntiDepBreakMode& Mode,
           RegClassVector& CriticalPathRCs) const {
  Mode = TargetSubtargetInfo::ANTIDEP_ALL;

  CriticalPathRCs.clear();

  if (isPPC64())
    CriticalPathRCs.push_back(&PPC::G8RCRegClass);
  else
    CriticalPathRCs.push_back(&PPC::GPRCRegClass);
    
  return OptLevel >= CodeGenOpt::Default;
}

Beispiel #6

Datei: TargetSubtargetInfo.cpp Projekt: johnjohnsp1/llvm-late-safepoint-placement

bool TargetSubtargetInfo::enablePostRAScheduler(
    CodeGenOpt::Level OptLevel,
    AntiDepBreakMode& Mode,
    RegClassVector& CriticalPathRCs) const {
    Mode = ANTIDEP_NONE;
    CriticalPathRCs.clear();
    return false;
}

Beispiel #7

Datei: SPUSubtarget.cpp Projekt: PhongNgo/llvm

/// Enable PostRA scheduling for optimization levels -O2 and -O3.
bool SPUSubtarget::enablePostRAScheduler(
                       CodeGenOpt::Level OptLevel,
                       TargetSubtargetInfo::AntiDepBreakMode& Mode,
                       RegClassVector& CriticalPathRCs) const {
  Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
  // CriticalPathsRCs seems to be the set of
  // RegisterClasses that antidep breakings are performed for.
  // Do it for all register classes 
  CriticalPathRCs.clear();
  CriticalPathRCs.push_back(&SPU::R8CRegClass);
  CriticalPathRCs.push_back(&SPU::R16CRegClass);
  CriticalPathRCs.push_back(&SPU::R32CRegClass);
  CriticalPathRCs.push_back(&SPU::R32FPRegClass);
  CriticalPathRCs.push_back(&SPU::R64CRegClass);
  CriticalPathRCs.push_back(&SPU::VECREGRegClass);
  return OptLevel >= CodeGenOpt::Default;
}

Beispiel #8

Datei: PPCSubtarget.cpp Projekt: AmesianX/llvm-othergen

void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
  CriticalPathRCs.clear();
  CriticalPathRCs.push_back(isPPC64() ?
                            &PPC::G8RCRegClass : &PPC::GPRCRegClass);
}

Beispiel #9

Datei: MipsSubtarget.cpp Projekt: eGit/llvm

void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
  CriticalPathRCs.clear();
  CriticalPathRCs.push_back(isGP64bit() ?
                            &Mips::GPR64RegClass : &Mips::GPR32RegClass);
}