void UDrawGraph::visit (SgNode * node) { using boost::lexical_cast; using std::string; file << newVertex (counter) << beginAttributes; switch (node->variantT ()) { case V_SgInitializedName: { SgInitializedName * castedNode = isSgInitializedName (node); file << setName (castedNode->get_name ().getString ()); break; } case V_SgVarRefExp: { SgVarRefExp * castedNode = isSgVarRefExp (node); file << setName (castedNode->get_symbol ()->get_name ().getString ()); file << setColor (RED); break; } case V_SgVariableDeclaration: { file << setName (node->class_name ()); file << setShape (RHOMBUS); break; } case V_SgIntVal: { SgIntVal * castedNode = isSgIntVal (node); file << setName (lexical_cast <string> (castedNode->get_value ())); file << setColor (GREEN); break; } case V_SgFloatVal: { SgFloatVal * castedNode = isSgFloatVal (node); file << setName (lexical_cast <string> (castedNode->get_value ())); file << setColor (GREEN); break; } case V_SgAddOp: { file << setName ("+"); file << setColor (YELLOW); break; } case V_SgMinusOp: case V_SgSubtractOp: { file << setName ("-"); file << setColor (YELLOW); break; } case V_SgMultiplyOp: { file << setName ("*"); file << setColor (YELLOW); break; } case V_SgDivideOp: { file << setName ("/"); file << setColor (YELLOW); break; } case V_SgAssignOp: { file << setName ("="); file << setColor (YELLOW); break; } case V_SgLessThanOp: { file << setName ("<"); file << setColor (YELLOW); break; } case V_SgLessOrEqualOp: { file << setName ("<="); file << setColor (YELLOW); break; } case V_SgGreaterThanOp: { file << setName (">"); file << setColor (YELLOW); break; } case V_SgGreaterOrEqualOp: { file << setName (">="); file << setColor (YELLOW); break; } case V_SgAddressOfOp: { file << setName ("&"); file << setColor (YELLOW); break; } default: { file << setName (node->class_name ()); break; } } file << endAttibutes << beginAttributes; if (counter != rootID) { SgNode * parent = node->get_parent (); unsigned int const parentID = nodes[parent]; file << newEdge << beginAttributes << setDirectionalLessEdge << endAttibutes << edgeLink (parentID) << endEdge; } file << endVertex; nodes[node] = counter; counter++; }
ExprSynAttr *examineExpr(SgExpression *expr, ostream &out) { stringstream ss1; stringstream ss2; stringstream ss3; SgExpression *e1; SgExpression *e2; SgBinaryOp *binop; SgUnaryOp *unaryop; SgType *type; ExprSynAttr *ret; ExprSynAttr *attr1, *attr2; string tmp_name; string tmp_type; string tmp2_name; string tmp2_type; if (expr == NULL) return NULL; ret = new ExprSynAttr(); attr1 = NULL; attr2 = NULL; switch(expr->variantT()) { /* Begin UnaryOp */ case V_SgMinusOp: out << "(-"; unaryop = isSgUnaryOp(expr); e1 = unaryop->get_operand(); attr1 = examineExpr(e1, out); out << ")"; ret->type = attr1->type; ret->sgtype = attr1->sgtype; ret->new_tmp_name(); ret->add_new_tmp_decl(ret->type, ret->result_var); ret->union_tmp_decls(attr1); ret->code << attr1->code.str(); ret->code << ret->result_var << "= -" << attr1->result_var; ret->code << ";" << endl; break; case V_SgUnaryAddOp: out << "(+"; unaryop = isSgUnaryOp(expr); e1 = unaryop->get_operand(); attr1 = examineExpr(e1, out); out << ")"; ret->type = attr1->type; ret->sgtype = attr1->sgtype; ret->new_tmp_name(); ret->add_new_tmp_decl(ret->type, ret->result_var); ret->union_tmp_decls(attr1); ret->code << attr1->code.str(); ret->code << ret->result_var << "= +" << attr1->result_var; ret->code << ";" << endl; break; case V_SgNotOp: out << "(!"; unaryop = isSgUnaryOp(expr); e1 = unaryop->get_operand(); attr1 = examineExpr(e1, out); out << ")"; ret->type = "int"; ret->sgtype = attr1->sgtype; ret->new_tmp_name(); ret->add_new_tmp_decl(ret->type, ret->result_var); ret->union_tmp_decls(attr1); ret->code << attr1->code.str(); ret->code << ret->result_var << "= (int)!" << attr1->result_var; ret->code << ";" << endl; break; case V_SgPointerDerefExp: out << "(*"; unaryop = isSgUnaryOp(expr); e1 = unaryop->get_operand(); attr1 = examineExpr(e1, out); out << ")"; ret->basetype(attr1); ret->new_tmp_name(); ret->add_new_tmp_decl(ret->type, ret->result_var); ret->union_tmp_decls(attr1); ret->code << attr1->code.str(); ret->code << ret->result_var << "= *" << attr1->result_var; ret->code << ";" << endl; break; case V_SgAddressOfOp: out << "(&"; unaryop = isSgUnaryOp(expr); e1 = unaryop->get_operand(); attr1 = examineExpr(e1, out); out << ")"; ret->type = attr1->type + "*"; /* FIXME ret->sgtype */ ret->new_tmp_name(); ret->add_new_tmp_decl(ret->type, ret->result_var); ret->union_tmp_decls(attr1); ret->code << attr1->code.str(); ret->code << ret->result_var << "= &" << attr1->result_var; ret->code << ";" << endl; break; case V_SgMinusMinusOp: unaryop = isSgUnaryOp(expr); if (unaryop->get_mode()) { out << "("; e1 = unaryop->get_operand(); attr1 = examineExpr(e1, out); out << "--)"; ret->type = attr1->type; ret->sgtype = attr1->sgtype; ret->new_tmp_name(); ret->add_new_tmp_decl(ret->type, ret->result_var); ret->union_tmp_decls(attr1); ret->code << attr1->code.str(); ret->code << ret->result_var << "=" << attr1->result_var << ";" << endl; ret->code << attr1->result_var << "=" << attr1->result_var << "-1;" << endl; } else { out << "(--"; e1 = unaryop->get_operand(); attr1 = examineExpr(e1, out); out << ")"; ret->type = attr1->type; ret->sgtype = attr1->sgtype; ret->result_var = attr1->result_var; ret->union_tmp_decls(attr1); ret->code << attr1->code.str(); ret->code << ret->result_var << "=" << attr1->result_var << "-1;" << endl; } break; case V_SgPlusPlusOp: unaryop = isSgUnaryOp(expr); if (unaryop->get_mode()) { out << "("; e1 = unaryop->get_operand(); attr1 = examineExpr(e1, out); out << "++)"; ret->type = attr1->type; ret->sgtype = attr1->sgtype; ret->new_tmp_name(); ret->add_new_tmp_decl(ret->type, ret->result_var); ret->union_tmp_decls(attr1); ret->code << attr1->code.str(); ret->code << ret->result_var << "=" << attr1->result_var << ";" << endl; ret->code << attr1->result_var << "=" << attr1->result_var << "+1;" << endl; } else { out << "(++"; e1 = unaryop->get_operand(); attr1 = examineExpr(e1, out); out << ")"; ret->type = attr1->type; ret->sgtype = attr1->sgtype; ret->result_var = attr1->result_var; ret->union_tmp_decls(attr1); ret->code << attr1->code.str(); ret->code << ret->result_var << "=" << attr1->result_var << "+1;" << endl; } break; case V_SgBitComplementOp: out << "(~"; unaryop = isSgUnaryOp(expr); e1 = unaryop->get_operand(); attr1 = examineExpr(e1, out); out << ")"; ret->type = attr1->type; ret->sgtype = attr1->sgtype; ret->new_tmp_name(); ret->add_new_tmp_decl(ret->type, ret->result_var); ret->union_tmp_decls(attr1); ret->code << attr1->code.str(); ret->code << ret->result_var << "= ~" << attr1->result_var; ret->code << ";" << endl; break; case V_SgCastExp: { out << "("; SgCastExp *castexp = isSgCastExp(expr); e1 = castexp->get_operand(); type = castexp->get_type(); examineType(type, out); out << ")"; attr1 = examineExpr(e1, out); stringstream casts; examineType(type, casts); ret->type = casts.str(); ret->sgtype = type; ret->new_tmp_name(tmp_name); ret->union_tmp_decls(attr1, NULL); ret->add_new_tmp_decl(ret->type, tmp_name); ret->result_var = tmp_name; ret->code << attr1->code.str() << tmp_name; ret->code << "=(" << ret->type << ")" << attr1->result_var; ret->code << ";" << endl; break; } /* End UnaryOp */ /* Begin BinaryOp */ case V_SgEqualityOp: binop = isSgBinaryOp(expr); e1 = binop->get_lhs_operand(); e2 = binop->get_rhs_operand(); out << "("; attr1 = examineExpr(e1, out); out << "=="; attr2 = examineExpr(e2, out); out << ")"; ret->type = "int"; ret->sgtype = attr1->sgtype; binop_noassign(ret, attr1, attr2, "=="); break; case V_SgLessThanOp: binop = isSgBinaryOp(expr); e1 = binop->get_lhs_operand(); e2 = binop->get_rhs_operand(); out << "("; attr1 = examineExpr(e1, out); out << "<"; attr2 = examineExpr(e2, out); out << ")"; ret->type = "int"; ret->sgtype = attr1->sgtype; binop_noassign(ret, attr1, attr2, "<"); break; case V_SgGreaterThanOp: binop = isSgBinaryOp(expr); e1 = binop->get_lhs_operand(); e2 = binop->get_rhs_operand(); out << "("; attr1 = examineExpr(e1, out); out << ">"; attr2 = examineExpr(e2, out); out << ")"; ret->type = "int"; ret->sgtype = attr1->sgtype; binop_noassign(ret, attr1, attr2, ">"); break; case V_SgNotEqualOp: binop = isSgBinaryOp(expr); e1 = binop->get_lhs_operand(); e2 = binop->get_rhs_operand(); out << "("; attr1 = examineExpr(e1, out); out << "!="; attr2 = examineExpr(e2, out); out << ")"; ret->type = "int"; ret->sgtype = attr1->sgtype; binop_noassign(ret, attr1, attr2, "!="); break; case V_SgLessOrEqualOp: binop = isSgBinaryOp(expr); e1 = binop->get_lhs_operand(); e2 = binop->get_rhs_operand(); out << "("; attr1 = examineExpr(e1, out); out << "<="; attr2 = examineExpr(e2, out); out << ")"; ret->type = "int"; ret->sgtype = attr1->sgtype; binop_noassign(ret, attr1, attr2, "<="); break; case V_SgGreaterOrEqualOp: binop = isSgBinaryOp(expr); e1 = binop->get_lhs_operand(); e2 = binop->get_rhs_operand(); out << "("; attr1 = examineExpr(e1, out); out << ">="; attr2 = examineExpr(e2, out); out << ")"; ret->type = "int"; ret->sgtype = attr1->sgtype; binop_noassign(ret, attr1, attr2, ">="); break; case V_SgAddOp: binop = isSgBinaryOp(expr); e1 = binop->get_lhs_operand(); e2 = binop->get_rhs_operand(); out << "("; attr1 = examineExpr(e1, out); out << "+"; attr2 = examineExpr(e2, out); out << ")"; ret->cast_type(attr1, attr2); binop_noassign(ret, attr1, attr2, "+"); break; case V_SgSubtractOp: binop = isSgBinaryOp(expr); e1 = binop->get_lhs_operand(); e2 = binop->get_rhs_operand(); out << "("; attr1 = examineExpr(e1, out); out << "-"; attr2 = examineExpr(e2, out); out << ")"; ret->cast_type(attr1, attr2); binop_noassign(ret, attr1, attr2, "-"); break; case V_SgMultiplyOp: binop = isSgBinaryOp(expr); e1 = binop->get_lhs_operand(); e2 = binop->get_rhs_operand(); out << "("; attr1 = examineExpr(e1, out); out << "*"; attr2 = examineExpr(e2, out); out << ")"; ret->cast_type(attr1, attr2); binop_noassign(ret, attr1, attr2, "*"); break; case V_SgDivideOp: binop = isSgBinaryOp(expr); e1 = binop->get_lhs_operand(); e2 = binop->get_rhs_operand(); out << "("; attr1 = examineExpr(e1, out); out << "/"; attr2 = examineExpr(e2, out); out << ")"; ret->cast_type(attr1, attr2); binop_noassign(ret, attr1, attr2, "/"); break; case V_SgIntegerDivideOp: binop = isSgBinaryOp(expr); e1 = binop->get_lhs_operand(); e2 = binop->get_rhs_operand(); out << "("; attr1 = examineExpr(e1, out); out << "/"; attr2 = examineExpr(e2, out); out << ")"; ret->cast_type(attr1, attr2); binop_noassign(ret, attr1, attr2, "/"); break; case V_SgModOp: binop = isSgBinaryOp(expr); e1 = binop->get_lhs_operand(); e2 = binop->get_rhs_operand(); out << "("; attr1 = examineExpr(e1, out); out << "%"; attr2 = examineExpr(e2, out); out << ")"; ret->cast_type(attr1, attr2); binop_noassign(ret, attr1, attr2, "%"); break; case V_SgAndOp: binop = isSgBinaryOp(expr); e1 = binop->get_lhs_operand(); e2 = binop->get_rhs_operand(); out << "("; attr1 = examineExpr(e1, out); out << "&&"; attr2 = examineExpr(e2, out); out << ")"; ret->cast_type(attr1, attr2); ret->type = "int"; binop_noassign(ret, attr1, attr2, "&&"); break; case V_SgOrOp: binop = isSgBinaryOp(expr); e1 = binop->get_lhs_operand(); e2 = binop->get_rhs_operand(); out << "("; attr1 = examineExpr(e1, out); out << "||"; attr2 = examineExpr(e2, out); out << ")"; ret->cast_type(attr1, attr2); ret->type = "int"; binop_noassign(ret, attr1, attr2, "||"); break; case V_SgBitXorOp: binop = isSgBinaryOp(expr); e1 = binop->get_lhs_operand(); e2 = binop->get_rhs_operand(); out << "("; attr1 = examineExpr(e1, out); out << "^"; attr2 = examineExpr(e2, out); out << ")"; ret->cast_type(attr1, attr2); binop_noassign(ret, attr1, attr2, "^"); break; case V_SgBitAndOp: binop = isSgBinaryOp(expr); e1 = binop->get_lhs_operand(); e2 = binop->get_rhs_operand(); out << "("; attr1 = examineExpr(e1, out); out << "&"; attr2 = examineExpr(e2, out); out << ")"; ret->cast_type(attr1, attr2); binop_noassign(ret, attr1, attr2, "&"); break; case V_SgBitOrOp: binop = isSgBinaryOp(expr); e1 = binop->get_lhs_operand(); e2 = binop->get_rhs_operand(); out << "("; attr1 = examineExpr(e1, out); out << "|"; attr2 = examineExpr(e2, out); out << ")"; ret->cast_type(attr1, attr2); binop_noassign(ret, attr1, attr2, "|"); break; case V_SgCommaOpExp: binop = isSgBinaryOp(expr); e1 = binop->get_lhs_operand(); e2 = binop->get_rhs_operand(); out << "("; attr1 = examineExpr(e1, out); out << ","; attr2 = examineExpr(e2, out); out << ")"; ret->cast_type(attr1, attr2); binop_noassign(ret, attr1, attr2, ","); break; case V_SgLshiftOp: binop = isSgBinaryOp(expr); e1 = binop->get_lhs_operand(); e2 = binop->get_rhs_operand(); out << "("; attr1 = examineExpr(e1, out); out << "<<"; attr2 = examineExpr(e2, out); out << ")"; ret->cast_type(attr1, attr2); binop_noassign(ret, attr1, attr2, "<<"); break; case V_SgRshiftOp: binop = isSgBinaryOp(expr); e1 = binop->get_lhs_operand(); e2 = binop->get_rhs_operand(); out << "("; attr1 = examineExpr(e1, out); out << ">>"; attr2 = examineExpr(e2, out); out << ")"; ret->cast_type(attr1, attr2); binop_noassign(ret, attr1, attr2, ">>"); break; case V_SgAssignOp: binop = isSgBinaryOp(expr); e1 = binop->get_lhs_operand(); e2 = binop->get_rhs_operand(); attr1 = examineExpr(e1, out); out << "="; attr2 = examineExpr(e2, out); ret->cast_type(attr1, attr2); ret->union_tmp_decls(attr1, attr2); ret->result_var = attr1->result_var; ret->code << attr2->code.str() << attr1->code.str() << ret->result_var; ret->code << "=" << attr2->result_var; ret->code << ";" << endl; break; case V_SgPlusAssignOp: binop = isSgBinaryOp(expr); e1 = binop->get_lhs_operand(); e2 = binop->get_rhs_operand(); attr1 = examineExpr(e1, out); out << "+="; attr2 = examineExpr(e2, out); ret->cast_type(attr1, attr2); ret = binop_assign(ret, attr1, attr2, "+"); break; case V_SgMinusAssignOp: binop = isSgBinaryOp(expr); e1 = binop->get_lhs_operand(); e2 = binop->get_rhs_operand(); attr1 = examineExpr(e1, out); out << "-="; attr2 = examineExpr(e2, out); ret->cast_type(attr1, attr2); ret = binop_assign(ret, attr1, attr2, "-"); break; case V_SgAndAssignOp: binop = isSgBinaryOp(expr); e1 = binop->get_lhs_operand(); e2 = binop->get_rhs_operand(); attr1 = examineExpr(e1, out); out << "&="; attr2 = examineExpr(e2, out); ret->cast_type(attr1, attr2); ret = binop_assign(ret, attr1, attr2, "&"); break; case V_SgIorAssignOp: binop = isSgBinaryOp(expr); e1 = binop->get_lhs_operand(); e2 = binop->get_rhs_operand(); attr1 = examineExpr(e1, out); out << "|="; attr2 = examineExpr(e2, out); ret->cast_type(attr1, attr2); ret = binop_assign(ret, attr1, attr2, "|"); break; case V_SgMultAssignOp: binop = isSgBinaryOp(expr); e1 = binop->get_lhs_operand(); e2 = binop->get_rhs_operand(); attr1 = examineExpr(e1, out); out << "*="; attr2 = examineExpr(e2, out); ret->cast_type(attr1, attr2); ret = binop_assign(ret, attr1, attr2, "*"); break; case V_SgDivAssignOp: binop = isSgBinaryOp(expr); e1 = binop->get_lhs_operand(); e2 = binop->get_rhs_operand(); attr1 = examineExpr(e1, out); out << "/="; attr2 = examineExpr(e2, out); ret->cast_type(attr1, attr2); ret = binop_assign(ret, attr1, attr2, "/"); break; case V_SgModAssignOp: binop = isSgBinaryOp(expr); e1 = binop->get_lhs_operand(); e2 = binop->get_rhs_operand(); attr1 = examineExpr(e1, out); out << "%="; attr2 = examineExpr(e2, out); ret->cast_type(attr1, attr2); ret = binop_assign(ret, attr1, attr2, "%"); break; case V_SgXorAssignOp: binop = isSgBinaryOp(expr); e1 = binop->get_lhs_operand(); e2 = binop->get_rhs_operand(); attr1 = examineExpr(e1, out); out << "^="; attr2 = examineExpr(e2, out); ret->cast_type(attr1, attr2); ret = binop_assign(ret, attr1, attr2, "^"); break; case V_SgLshiftAssignOp: binop = isSgBinaryOp(expr); e1 = binop->get_lhs_operand(); e2 = binop->get_rhs_operand(); attr1 = examineExpr(e1, out); out << "<<="; attr2 = examineExpr(e2, out); ret->cast_type(attr1, attr2); ret = binop_assign(ret, attr1, attr2, "<<"); break; case V_SgRshiftAssignOp: binop = isSgBinaryOp(expr); e1 = binop->get_lhs_operand(); e2 = binop->get_rhs_operand(); attr1 = examineExpr(e1, out); out << ">>="; attr2 = examineExpr(e2, out); ret->cast_type(attr1, attr2); ret = binop_assign(ret, attr1, attr2, ">>"); break; case V_SgExponentiationOp: binop = isSgBinaryOp(expr); e1 = binop->get_lhs_operand(); e2 = binop->get_rhs_operand(); out << "("; attr1 = examineExpr(e1, out); out << "ExpUnknown"; attr2 = examineExpr(e2, out); out << ")"; break; case V_SgConcatenationOp: binop = isSgBinaryOp(expr); e1 = binop->get_lhs_operand(); e2 = binop->get_rhs_operand(); out << "("; attr1 = examineExpr(e1, out); out << "CatUnknown"; attr2 = examineExpr(e2, out); out << ")"; break; case V_SgPntrArrRefExp: { binop = isSgBinaryOp(expr); e1 = binop->get_lhs_operand(); e2 = binop->get_rhs_operand(); attr1 = examineExpr(e1, out); out << "["; attr2 = examineExpr(e2, out); out << "]"; ret->basetype(attr1); ret->union_tmp_decls(attr1, attr2); ret->result_var = attr1->result_var + "[" + attr2->result_var + "]"; ret->code << attr1->code.str() << attr2->code.str(); break; } /* End BinaryOp */ /* Begin variables */ case V_SgVarRefExp: { stringstream casts; SgVarRefExp *varref = isSgVarRefExp(expr); if (NULL == varref) return NULL; SgVariableSymbol *svsym = varref->get_symbol(); if (NULL == svsym) return NULL; out << svsym->get_name().getString(); ret->result_var = svsym->get_name().getString(); examineType(svsym->get_type(), casts); ret->type = casts.str(); ret->sgtype = svsym->get_type(); /* ret->new_tmp_name(); examineType(svsym->get_type(), casts); ret->type = casts.str(); ret->sgtype = svsym->get_type(); ret->add_new_tmp_decl(ret->type, ret->result_var); ret->code << ret->result_var << " = " << svsym->get_name().getString(); ret->code << ";" << endl; */ break; } case V_SgLabelRefExp: SgLabelRefExp *labref = isSgLabelRefExp(expr); out << labref->get_name().getString(); break; /* Begin Constants */ case V_SgIntVal: { stringstream casts; SgIntVal *intval = isSgIntVal(expr); out << intval->get_value(); casts << intval->get_value(); ret->result_var = casts.str(); ret->type = "int"; ret->sgtype = intval->get_type(); break; } case V_SgLongIntVal: { stringstream casts; SgLongIntVal *longval = isSgLongIntVal(expr); out << longval->get_value() << "L"; casts << longval->get_value() << "L"; ret->result_var = casts.str(); ret->type = "long"; ret->sgtype = longval->get_type(); break; } case V_SgUnsignedIntVal: { stringstream casts; SgUnsignedIntVal *uintval = isSgUnsignedIntVal(expr); out << uintval->get_value() << "U"; casts << uintval->get_value() << "U"; ret->result_var = casts.str(); ret->type = "unsigned"; ret->sgtype = uintval->get_type(); break; } case V_SgUnsignedLongVal: { stringstream casts; SgUnsignedLongVal *ulongval = isSgUnsignedLongVal(expr); out << ulongval->get_value() << "UL"; casts << ulongval->get_value() << "UL"; ret->result_var = casts.str(); ret->type = "unsigned long"; ret->sgtype = ulongval->get_type(); break; } case V_SgDoubleVal: { stringstream casts; SgDoubleVal *doubleval = isSgDoubleVal(expr); out << doubleval->get_value(); casts << doubleval->get_value(); ret->result_var = casts.str(); ret->type = "double"; ret->sgtype = doubleval->get_type(); break; } case V_SgFloatVal: { stringstream casts; SgFloatVal *floatval = isSgFloatVal(expr); out << floatval->get_value(); casts << floatval->get_value(); ret->result_var = casts.str(); ret->type = "float"; ret->sgtype = floatval->get_type(); break; } default: out << "/* UNKNOWN EXPR[" << expr->class_name() << "](" << expr->variantT() << ") " << expr->unparseToString() << " */" << endl; cerr << "UNKNOWN EXPR[" << expr->class_name() << "] " << expr->unparseToString() << endl; break; } if (NULL != attr1) delete attr1; if (NULL != attr2) delete attr2; return ret; }