bool
ABIMacOSX_arm::CreateFunctionEntryUnwindPlan (UnwindPlan &unwind_plan)
{
uint32_t reg_kind = unwind_plan.GetRegisterKind();
uint32_t lr_reg_num = LLDB_INVALID_REGNUM;
uint32_t sp_reg_num = LLDB_INVALID_REGNUM;
uint32_t pc_reg_num = LLDB_INVALID_REGNUM;
switch (reg_kind)
{
case eRegisterKindDWARF:
case eRegisterKindGCC:
lr_reg_num = dwarf_lr;
sp_reg_num = dwarf_sp;
pc_reg_num = dwarf_pc;
break;
case eRegisterKindGeneric:
lr_reg_num = LLDB_REGNUM_GENERIC_RA;
sp_reg_num = LLDB_REGNUM_GENERIC_SP;
pc_reg_num = LLDB_REGNUM_GENERIC_PC;
break;
}
if (lr_reg_num == LLDB_INVALID_REGNUM ||
sp_reg_num == LLDB_INVALID_REGNUM ||
pc_reg_num == LLDB_INVALID_REGNUM)
return false;
UnwindPlan::RowSP row(new UnwindPlan::Row);
// Our Call Frame Address is the stack pointer value
row->SetCFARegister (sp_reg_num);
// The previous PC is in the LR
row->SetRegisterLocationToRegister(pc_reg_num, lr_reg_num, true);
unwind_plan.AppendRow (row);
// All other registers are the same.
unwind_plan.SetSourceName ("arm at-func-entry default");
unwind_plan.SetSourcedFromCompiler (eLazyBoolNo);
return true;
}
bool
UnwindAssemblyInstEmulation::GetNonCallSiteUnwindPlanFromAssembly (AddressRange& range,
Thread& thread,
UnwindPlan& unwind_plan)
{
if (range.GetByteSize() > 0 &&
range.GetBaseAddress().IsValid() &&
m_inst_emulator_ap.get())
{
// The instruction emulation subclass setup the unwind plan for the
// first instruction.
m_inst_emulator_ap->CreateFunctionEntryUnwind (unwind_plan);
// CreateFunctionEntryUnwind should have created the first row. If it
// doesn't, then we are done.
if (unwind_plan.GetRowCount() == 0)
return false;
ExecutionContext exe_ctx;
thread.CalculateExecutionContext(exe_ctx);
const bool prefer_file_cache = true;
DisassemblerSP disasm_sp (Disassembler::DisassembleRange (m_arch,
NULL,
NULL,
exe_ctx,
range,
prefer_file_cache));
Log *log(GetLogIfAllCategoriesSet (LIBLLDB_LOG_UNWIND));
if (disasm_sp)
{
m_range_ptr = ⦥
m_thread_ptr = &thread;
m_unwind_plan_ptr = &unwind_plan;
const uint32_t addr_byte_size = m_arch.GetAddressByteSize();
const bool show_address = true;
const bool show_bytes = true;
m_inst_emulator_ap->GetRegisterInfo (unwind_plan.GetRegisterKind(),
unwind_plan.GetInitialCFARegister(),
m_cfa_reg_info);
m_fp_is_cfa = false;
m_register_values.clear();
m_pushed_regs.clear();
// Initialize the CFA with a known value. In the 32 bit case
// it will be 0x80000000, and in the 64 bit case 0x8000000000000000.
// We use the address byte size to be safe for any future address sizes
m_initial_sp = (1ull << ((addr_byte_size * 8) - 1));
RegisterValue cfa_reg_value;
cfa_reg_value.SetUInt (m_initial_sp, m_cfa_reg_info.byte_size);
SetRegisterValue (m_cfa_reg_info, cfa_reg_value);
const InstructionList &inst_list = disasm_sp->GetInstructionList ();
const size_t num_instructions = inst_list.GetSize();
if (num_instructions > 0)
{
Instruction *inst = inst_list.GetInstructionAtIndex (0).get();
const lldb::addr_t base_addr = inst->GetAddress().GetFileAddress();
// Map for storing the unwind plan row and the value of the registers at a given offset.
// When we see a forward branch we add a new entry to this map with the actual unwind plan
// row and register context for the target address of the branch as the current data have
// to be valid for the target address of the branch too if we are in the same function.
std::map<lldb::addr_t, std::pair<UnwindPlan::RowSP, RegisterValueMap>> saved_unwind_states;
// Make a copy of the current instruction Row and save it in m_curr_row
// so we can add updates as we process the instructions.
UnwindPlan::RowSP last_row = unwind_plan.GetLastRow();
UnwindPlan::Row *newrow = new UnwindPlan::Row;
if (last_row.get())
*newrow = *last_row.get();
m_curr_row.reset(newrow);
// Add the initial state to the save list with offset 0.
saved_unwind_states.insert({0, {last_row, m_register_values}});
// cache the pc register number (in whatever register numbering this UnwindPlan uses) for
// quick reference during instruction parsing.
uint32_t pc_reg_num = LLDB_INVALID_REGNUM;
RegisterInfo pc_reg_info;
if (m_inst_emulator_ap->GetRegisterInfo (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, pc_reg_info))
pc_reg_num = pc_reg_info.kinds[unwind_plan.GetRegisterKind()];
else
pc_reg_num = LLDB_INVALID_REGNUM;
// cache the return address register number (in whatever register numbering this UnwindPlan uses) for
// quick reference during instruction parsing.
uint32_t ra_reg_num = LLDB_INVALID_REGNUM;
RegisterInfo ra_reg_info;
if (m_inst_emulator_ap->GetRegisterInfo (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, ra_reg_info))
ra_reg_num = ra_reg_info.kinds[unwind_plan.GetRegisterKind()];
else
ra_reg_num = LLDB_INVALID_REGNUM;
for (size_t idx=0; idx<num_instructions; ++idx)
{
m_curr_row_modified = false;
m_forward_branch_offset = 0;
inst = inst_list.GetInstructionAtIndex (idx).get();
if (inst)
{
lldb::addr_t current_offset = inst->GetAddress().GetFileAddress() - base_addr;
auto it = saved_unwind_states.upper_bound(current_offset);
assert(it != saved_unwind_states.begin() && "Unwind row for the function entry missing");
--it; // Move it to the row corresponding to the current offset
// If the offset of m_curr_row don't match with the offset we see in saved_unwind_states
// then we have to update m_curr_row and m_register_values based on the saved values. It
// is happenning after we processed an epilogue and a return to caller instruction.
if (it->second.first->GetOffset() != m_curr_row->GetOffset())
{
UnwindPlan::Row *newrow = new UnwindPlan::Row;
*newrow = *it->second.first;
m_curr_row.reset(newrow);
m_register_values = it->second.second;;
}
if (log && log->GetVerbose ())
{
StreamString strm;
lldb_private::FormatEntity::Entry format;
FormatEntity::Parse("${frame.pc}: ", format);
inst->Dump(&strm, inst_list.GetMaxOpcocdeByteSize (), show_address, show_bytes, NULL, NULL, NULL, &format, 0);
log->PutCString (strm.GetData());
}
m_inst_emulator_ap->SetInstruction (inst->GetOpcode(),
inst->GetAddress(),
exe_ctx.GetTargetPtr());
m_inst_emulator_ap->EvaluateInstruction (eEmulateInstructionOptionIgnoreConditions);
// If the current instruction is a branch forward then save the current CFI information
// for the offset where we are branching.
if (m_forward_branch_offset != 0 && range.ContainsFileAddress(inst->GetAddress().GetFileAddress() + m_forward_branch_offset))
{
auto newrow = std::make_shared<UnwindPlan::Row>(*m_curr_row.get());
newrow->SetOffset(current_offset + m_forward_branch_offset);
saved_unwind_states.insert({current_offset + m_forward_branch_offset, {newrow, m_register_values}});
unwind_plan.InsertRow(newrow);
}
// Were there any changes to the CFI while evaluating this instruction?
if (m_curr_row_modified)
{
// Save the modified row if we don't already have a CFI row in the currennt address
if (saved_unwind_states.count(current_offset + inst->GetOpcode().GetByteSize()) == 0)
{
m_curr_row->SetOffset (current_offset + inst->GetOpcode().GetByteSize());
unwind_plan.InsertRow (m_curr_row);
saved_unwind_states.insert({current_offset + inst->GetOpcode().GetByteSize(), {m_curr_row, m_register_values}});
// Allocate a new Row for m_curr_row, copy the current state into it
UnwindPlan::Row *newrow = new UnwindPlan::Row;
*newrow = *m_curr_row.get();
m_curr_row.reset(newrow);
}
}
}
}
}
// FIXME: The DisassemblerLLVMC has a reference cycle and won't go away if it has any active instructions.
// I'll fix that but for now, just clear the list and it will go away nicely.
disasm_sp->GetInstructionList().Clear();
}
if (log && log->GetVerbose ())
{
StreamString strm;
lldb::addr_t base_addr = range.GetBaseAddress().GetLoadAddress(thread.CalculateTarget().get());
strm.Printf ("Resulting unwind rows for [0x%" PRIx64 " - 0x%" PRIx64 "):", base_addr, base_addr + range.GetByteSize());
unwind_plan.Dump(strm, &thread, base_addr);
log->PutCString (strm.GetData());
}
return unwind_plan.GetRowCount() > 0;
}
return false;
}
bool UnwindAssembly_x86::AugmentUnwindPlanFromCallSite(
AddressRange &func, Thread &thread, UnwindPlan &unwind_plan) {
bool do_augment_unwindplan = true;
UnwindPlan::RowSP first_row = unwind_plan.GetRowForFunctionOffset(0);
UnwindPlan::RowSP last_row = unwind_plan.GetRowForFunctionOffset(-1);
int wordsize = 8;
ProcessSP process_sp(thread.GetProcess());
if (process_sp.get() == nullptr)
return false;
wordsize = process_sp->GetTarget().GetArchitecture().GetAddressByteSize();
RegisterNumber sp_regnum(thread, eRegisterKindGeneric,
LLDB_REGNUM_GENERIC_SP);
RegisterNumber pc_regnum(thread, eRegisterKindGeneric,
LLDB_REGNUM_GENERIC_PC);
// Does this UnwindPlan describe the prologue? I want to see that the CFA is
// set in terms of the stack pointer plus an offset, and I want to see that
// rip is retrieved at the CFA-wordsize. If there is no description of the
// prologue, don't try to augment this eh_frame unwinder code, fall back to
// assembly parsing instead.
if (first_row->GetCFAValue().GetValueType() !=
UnwindPlan::Row::FAValue::isRegisterPlusOffset ||
RegisterNumber(thread, unwind_plan.GetRegisterKind(),
first_row->GetCFAValue().GetRegisterNumber()) !=
sp_regnum ||
first_row->GetCFAValue().GetOffset() != wordsize) {
return false;
}
UnwindPlan::Row::RegisterLocation first_row_pc_loc;
if (!first_row->GetRegisterInfo(
pc_regnum.GetAsKind(unwind_plan.GetRegisterKind()),
first_row_pc_loc) ||
!first_row_pc_loc.IsAtCFAPlusOffset() ||
first_row_pc_loc.GetOffset() != -wordsize) {
return false;
}
// It looks like the prologue is described. Is the epilogue described? If it
// is, no need to do any augmentation.
if (first_row != last_row &&
first_row->GetOffset() != last_row->GetOffset()) {
// The first & last row have the same CFA register and the same CFA offset
// value and the CFA register is esp/rsp (the stack pointer).
// We're checking that both of them have an unwind rule like "CFA=esp+4" or
// CFA+rsp+8".
if (first_row->GetCFAValue().GetValueType() ==
last_row->GetCFAValue().GetValueType() &&
first_row->GetCFAValue().GetRegisterNumber() ==
last_row->GetCFAValue().GetRegisterNumber() &&
first_row->GetCFAValue().GetOffset() ==
last_row->GetCFAValue().GetOffset()) {
// Get the register locations for eip/rip from the first & last rows. Are
// they both CFA plus an offset? Is it the same offset?
UnwindPlan::Row::RegisterLocation last_row_pc_loc;
if (last_row->GetRegisterInfo(
pc_regnum.GetAsKind(unwind_plan.GetRegisterKind()),
last_row_pc_loc)) {
if (last_row_pc_loc.IsAtCFAPlusOffset() &&
first_row_pc_loc.GetOffset() == last_row_pc_loc.GetOffset()) {
// One last sanity check: Is the unwind rule for getting the caller
// pc value "deref the CFA-4" or "deref the CFA-8"?
// If so, we have an UnwindPlan that already describes the epilogue
// and we don't need to modify it at all.
if (first_row_pc_loc.GetOffset() == -wordsize) {
do_augment_unwindplan = false;
}
}
}
}
}
if (do_augment_unwindplan) {
if (!func.GetBaseAddress().IsValid() || func.GetByteSize() == 0)
return false;
if (m_assembly_inspection_engine == nullptr)
return false;
const bool prefer_file_cache = true;
std::vector<uint8_t> function_text(func.GetByteSize());
Status error;
if (process_sp->GetTarget().ReadMemory(
func.GetBaseAddress(), prefer_file_cache, function_text.data(),
func.GetByteSize(), error) == func.GetByteSize()) {
RegisterContextSP reg_ctx(thread.GetRegisterContext());
m_assembly_inspection_engine->Initialize(reg_ctx);
return m_assembly_inspection_engine->AugmentUnwindPlanFromCallSite(
function_text.data(), func.GetByteSize(), func, unwind_plan, reg_ctx);
}
}
return false;
}
bool UnwindAssemblyInstEmulation::GetNonCallSiteUnwindPlanFromAssembly(
AddressRange &range, uint8_t *opcode_data, size_t opcode_size,
UnwindPlan &unwind_plan) {
if (opcode_data == nullptr || opcode_size == 0)
return false;
if (range.GetByteSize() > 0 && range.GetBaseAddress().IsValid() &&
m_inst_emulator_ap.get()) {
// The instruction emulation subclass setup the unwind plan for the
// first instruction.
m_inst_emulator_ap->CreateFunctionEntryUnwind(unwind_plan);
// CreateFunctionEntryUnwind should have created the first row. If it
// doesn't, then we are done.
if (unwind_plan.GetRowCount() == 0)
return false;
const bool prefer_file_cache = true;
DisassemblerSP disasm_sp(Disassembler::DisassembleBytes(
m_arch, NULL, NULL, range.GetBaseAddress(), opcode_data, opcode_size,
99999, prefer_file_cache));
Log *log(GetLogIfAllCategoriesSet(LIBLLDB_LOG_UNWIND));
if (disasm_sp) {
m_range_ptr = ⦥
m_unwind_plan_ptr = &unwind_plan;
const uint32_t addr_byte_size = m_arch.GetAddressByteSize();
const bool show_address = true;
const bool show_bytes = true;
m_inst_emulator_ap->GetRegisterInfo(unwind_plan.GetRegisterKind(),
unwind_plan.GetInitialCFARegister(),
m_cfa_reg_info);
m_fp_is_cfa = false;
m_register_values.clear();
m_pushed_regs.clear();
// Initialize the CFA with a known value. In the 32 bit case
// it will be 0x80000000, and in the 64 bit case 0x8000000000000000.
// We use the address byte size to be safe for any future address sizes
m_initial_sp = (1ull << ((addr_byte_size * 8) - 1));
RegisterValue cfa_reg_value;
cfa_reg_value.SetUInt(m_initial_sp, m_cfa_reg_info.byte_size);
SetRegisterValue(m_cfa_reg_info, cfa_reg_value);
const InstructionList &inst_list = disasm_sp->GetInstructionList();
const size_t num_instructions = inst_list.GetSize();
if (num_instructions > 0) {
Instruction *inst = inst_list.GetInstructionAtIndex(0).get();
const lldb::addr_t base_addr = inst->GetAddress().GetFileAddress();
// Map for storing the unwind plan row and the value of the registers at
// a given offset.
// When we see a forward branch we add a new entry to this map with the
// actual unwind plan
// row and register context for the target address of the branch as the
// current data have
// to be valid for the target address of the branch too if we are in the
// same function.
std::map<lldb::addr_t, std::pair<UnwindPlan::RowSP, RegisterValueMap>>
saved_unwind_states;
// Make a copy of the current instruction Row and save it in m_curr_row
// so we can add updates as we process the instructions.
UnwindPlan::RowSP last_row = unwind_plan.GetLastRow();
UnwindPlan::Row *newrow = new UnwindPlan::Row;
if (last_row.get())
*newrow = *last_row.get();
m_curr_row.reset(newrow);
// Add the initial state to the save list with offset 0.
saved_unwind_states.insert({0, {last_row, m_register_values}});
// cache the pc register number (in whatever register numbering this
// UnwindPlan uses) for
// quick reference during instruction parsing.
RegisterInfo pc_reg_info;
m_inst_emulator_ap->GetRegisterInfo(
eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, pc_reg_info);
// cache the return address register number (in whatever register
// numbering this UnwindPlan uses) for
// quick reference during instruction parsing.
RegisterInfo ra_reg_info;
m_inst_emulator_ap->GetRegisterInfo(
eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, ra_reg_info);
// The architecture dependent condition code of the last processed
// instruction.
EmulateInstruction::InstructionCondition last_condition =
EmulateInstruction::UnconditionalCondition;
lldb::addr_t condition_block_start_offset = 0;
for (size_t idx = 0; idx < num_instructions; ++idx) {
m_curr_row_modified = false;
m_forward_branch_offset = 0;
inst = inst_list.GetInstructionAtIndex(idx).get();
if (inst) {
lldb::addr_t current_offset =
inst->GetAddress().GetFileAddress() - base_addr;
auto it = saved_unwind_states.upper_bound(current_offset);
assert(it != saved_unwind_states.begin() &&
"Unwind row for the function entry missing");
--it; // Move it to the row corresponding to the current offset
// If the offset of m_curr_row don't match with the offset we see in
// saved_unwind_states
// then we have to update m_curr_row and m_register_values based on
// the saved values. It
// is happenning after we processed an epilogue and a return to
// caller instruction.
if (it->second.first->GetOffset() != m_curr_row->GetOffset()) {
UnwindPlan::Row *newrow = new UnwindPlan::Row;
*newrow = *it->second.first;
m_curr_row.reset(newrow);
m_register_values = it->second.second;
}
m_inst_emulator_ap->SetInstruction(inst->GetOpcode(),
inst->GetAddress(), nullptr);
if (last_condition !=
m_inst_emulator_ap->GetInstructionCondition()) {
if (m_inst_emulator_ap->GetInstructionCondition() !=
EmulateInstruction::UnconditionalCondition &&
saved_unwind_states.count(current_offset) == 0) {
// If we don't have a saved row for the current offset then save
// our
// current state because we will have to restore it after the
// conditional block.
auto new_row =
std::make_shared<UnwindPlan::Row>(*m_curr_row.get());
saved_unwind_states.insert(
{current_offset, {new_row, m_register_values}});
}
// If the last instruction was conditional with a different
// condition
// then the then current condition then restore the condition.
if (last_condition !=
EmulateInstruction::UnconditionalCondition) {
const auto &saved_state =
saved_unwind_states.at(condition_block_start_offset);
m_curr_row =
std::make_shared<UnwindPlan::Row>(*saved_state.first);
m_curr_row->SetOffset(current_offset);
m_register_values = saved_state.second;
bool replace_existing =
true; // The last instruction might already
// created a row for this offset and
// we want to overwrite it.
unwind_plan.InsertRow(
std::make_shared<UnwindPlan::Row>(*m_curr_row),
replace_existing);
}
// We are starting a new conditional block at the catual offset
condition_block_start_offset = current_offset;
}
if (log && log->GetVerbose()) {
StreamString strm;
lldb_private::FormatEntity::Entry format;
FormatEntity::Parse("${frame.pc}: ", format);
inst->Dump(&strm, inst_list.GetMaxOpcocdeByteSize(), show_address,
show_bytes, NULL, NULL, NULL, &format, 0);
log->PutString(strm.GetString());
}
last_condition = m_inst_emulator_ap->GetInstructionCondition();
m_inst_emulator_ap->EvaluateInstruction(
eEmulateInstructionOptionIgnoreConditions);
// If the current instruction is a branch forward then save the
// current CFI information
// for the offset where we are branching.
if (m_forward_branch_offset != 0 &&
range.ContainsFileAddress(inst->GetAddress().GetFileAddress() +
m_forward_branch_offset)) {
auto newrow =
std::make_shared<UnwindPlan::Row>(*m_curr_row.get());
newrow->SetOffset(current_offset + m_forward_branch_offset);
saved_unwind_states.insert(
{current_offset + m_forward_branch_offset,
{newrow, m_register_values}});
unwind_plan.InsertRow(newrow);
}
// Were there any changes to the CFI while evaluating this
// instruction?
if (m_curr_row_modified) {
// Save the modified row if we don't already have a CFI row in the
// currennt address
if (saved_unwind_states.count(
current_offset + inst->GetOpcode().GetByteSize()) == 0) {
m_curr_row->SetOffset(current_offset +
inst->GetOpcode().GetByteSize());
unwind_plan.InsertRow(m_curr_row);
saved_unwind_states.insert(
{current_offset + inst->GetOpcode().GetByteSize(),
{m_curr_row, m_register_values}});
// Allocate a new Row for m_curr_row, copy the current state
// into it
UnwindPlan::Row *newrow = new UnwindPlan::Row;
*newrow = *m_curr_row.get();
m_curr_row.reset(newrow);
}
}
}
}
}
}
if (log && log->GetVerbose()) {
StreamString strm;
lldb::addr_t base_addr = range.GetBaseAddress().GetFileAddress();
strm.Printf("Resulting unwind rows for [0x%" PRIx64 " - 0x%" PRIx64 "):",
base_addr, base_addr + range.GetByteSize());
unwind_plan.Dump(strm, nullptr, base_addr);
log->PutString(strm.GetString());
}
return unwind_plan.GetRowCount() > 0;
}
return false;
}
bool
UnwindAssemblyInstEmulation::GetNonCallSiteUnwindPlanFromAssembly (AddressRange& range,
Thread& thread,
UnwindPlan& unwind_plan)
{
if (range.GetByteSize() > 0 &&
range.GetBaseAddress().IsValid() &&
m_inst_emulator_ap.get())
{
// The the instruction emulation subclass setup the unwind plan for the
// first instruction.
m_inst_emulator_ap->CreateFunctionEntryUnwind (unwind_plan);
// CreateFunctionEntryUnwind should have created the first row. If it
// doesn't, then we are done.
if (unwind_plan.GetRowCount() == 0)
return false;
ExecutionContext exe_ctx;
thread.CalculateExecutionContext(exe_ctx);
DisassemblerSP disasm_sp (Disassembler::DisassembleRange (m_arch,
NULL,
exe_ctx,
range));
LogSP log(GetLogIfAllCategoriesSet (LIBLLDB_LOG_UNWIND));
if (disasm_sp)
{
m_range_ptr = ⦥
m_thread_ptr = &thread;
m_unwind_plan_ptr = &unwind_plan;
const uint32_t addr_byte_size = m_arch.GetAddressByteSize();
const bool show_address = true;
const bool show_bytes = true;
const bool raw = false;
// Initialize the CFA with a known value. In the 32 bit case
// it will be 0x80000000, and in the 64 bit case 0x8000000000000000.
// We use the address byte size to be safe for any future addresss sizes
m_inst_emulator_ap->GetRegisterInfo (unwind_plan.GetRegisterKind(),
unwind_plan.GetInitialCFARegister(),
m_cfa_reg_info);
m_fp_is_cfa = false;
m_register_values.clear();
m_pushed_regs.clear();
m_initial_sp = (1ull << ((addr_byte_size * 8) - 1));
RegisterValue cfa_reg_value;
cfa_reg_value.SetUInt (m_initial_sp, m_cfa_reg_info.byte_size);
SetRegisterValue (m_cfa_reg_info, cfa_reg_value);
const InstructionList &inst_list = disasm_sp->GetInstructionList ();
const size_t num_instructions = inst_list.GetSize();
if (num_instructions > 0)
{
Instruction *inst = inst_list.GetInstructionAtIndex (0).get();
const addr_t base_addr = inst->GetAddress().GetFileAddress();
// Initialize the current row with the one row that was created
// from the CreateFunctionEntryUnwind call above...
m_curr_row = unwind_plan.GetLastRow();
for (size_t idx=0; idx<num_instructions; ++idx)
{
inst = inst_list.GetInstructionAtIndex (idx).get();
if (inst)
{
if (log && log->GetVerbose ())
{
StreamString strm;
inst->Dump(&strm, inst_list.GetMaxOpcocdeByteSize (), show_address, show_bytes, &exe_ctx, raw);
log->PutCString (strm.GetData());
}
m_inst_emulator_ap->SetInstruction (inst->GetOpcode(),
inst->GetAddress(),
exe_ctx.GetTargetPtr());
m_inst_emulator_ap->EvaluateInstruction (eEmulateInstructionOptionIgnoreConditions);
if (unwind_plan.GetLastRow() != m_curr_row)
{
// Be sure to not edit the offset unless our row has changed
// so that the "!=" call above doesn't trigger every time
m_curr_row.SetOffset (inst->GetAddress().GetFileAddress() + inst->GetOpcode().GetByteSize() - base_addr);
// Append the new row
unwind_plan.AppendRow (m_curr_row);
}
}
}
}
}
if (log && log->GetVerbose ())
{
StreamString strm;
lldb::addr_t base_addr = range.GetBaseAddress().GetLoadAddress(&thread.GetProcess().GetTarget());
strm.Printf ("Resulting unwind rows for [0x%llx - 0x%llx):", base_addr, base_addr + range.GetByteSize());
unwind_plan.Dump(strm, &thread, base_addr);
log->PutCString (strm.GetData());
}
return unwind_plan.GetRowCount() > 0;
}
return false;
}
bool
UnwindAssemblyInstEmulation::GetNonCallSiteUnwindPlanFromAssembly (AddressRange& range,
Thread& thread,
UnwindPlan& unwind_plan)
{
if (range.GetByteSize() > 0 &&
range.GetBaseAddress().IsValid() &&
m_inst_emulator_ap.get())
{
// The instruction emulation subclass setup the unwind plan for the
// first instruction.
m_inst_emulator_ap->CreateFunctionEntryUnwind (unwind_plan);
// CreateFunctionEntryUnwind should have created the first row. If it
// doesn't, then we are done.
if (unwind_plan.GetRowCount() == 0)
return false;
ExecutionContext exe_ctx;
thread.CalculateExecutionContext(exe_ctx);
const bool prefer_file_cache = true;
DisassemblerSP disasm_sp (Disassembler::DisassembleRange (m_arch,
NULL,
NULL,
exe_ctx,
range,
prefer_file_cache));
Log *log(GetLogIfAllCategoriesSet (LIBLLDB_LOG_UNWIND));
if (disasm_sp)
{
m_range_ptr = ⦥
m_thread_ptr = &thread;
m_unwind_plan_ptr = &unwind_plan;
const uint32_t addr_byte_size = m_arch.GetAddressByteSize();
const bool show_address = true;
const bool show_bytes = true;
m_inst_emulator_ap->GetRegisterInfo (unwind_plan.GetRegisterKind(),
unwind_plan.GetInitialCFARegister(),
m_cfa_reg_info);
m_fp_is_cfa = false;
m_register_values.clear();
m_pushed_regs.clear();
// Initialize the CFA with a known value. In the 32 bit case
// it will be 0x80000000, and in the 64 bit case 0x8000000000000000.
// We use the address byte size to be safe for any future address sizes
m_initial_sp = (1ull << ((addr_byte_size * 8) - 1));
RegisterValue cfa_reg_value;
cfa_reg_value.SetUInt (m_initial_sp, m_cfa_reg_info.byte_size);
SetRegisterValue (m_cfa_reg_info, cfa_reg_value);
const InstructionList &inst_list = disasm_sp->GetInstructionList ();
const size_t num_instructions = inst_list.GetSize();
if (num_instructions > 0)
{
Instruction *inst = inst_list.GetInstructionAtIndex (0).get();
const addr_t base_addr = inst->GetAddress().GetFileAddress();
// Make a copy of the current instruction Row and save it in m_curr_row
// so we can add updates as we process the instructions.
UnwindPlan::RowSP last_row = unwind_plan.GetLastRow();
UnwindPlan::Row *newrow = new UnwindPlan::Row;
if (last_row.get())
*newrow = *last_row.get();
m_curr_row.reset(newrow);
// Once we've seen the initial prologue instructions complete, save a
// copy of the CFI at that point into prologue_completed_row for possible
// use later.
int instructions_since_last_prologue_insn = 0; // # of insns since last CFI was update
bool reinstate_prologue_next_instruction = false; // Next iteration, re-install the prologue row of CFI
bool last_instruction_restored_return_addr_reg = false; // re-install the prologue row of CFI if the next instruction is a branch immediate
bool return_address_register_has_been_saved = false; // if we've seen the ra register get saved yet
UnwindPlan::RowSP prologue_completed_row; // copy of prologue row of CFI
// cache the pc register number (in whatever register numbering this UnwindPlan uses) for
// quick reference during instruction parsing.
uint32_t pc_reg_num = LLDB_INVALID_REGNUM;
RegisterInfo pc_reg_info;
if (m_inst_emulator_ap->GetRegisterInfo (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, pc_reg_info))
pc_reg_num = pc_reg_info.kinds[unwind_plan.GetRegisterKind()];
else
pc_reg_num = LLDB_INVALID_REGNUM;
// cache the return address register number (in whatever register numbering this UnwindPlan uses) for
// quick reference during instruction parsing.
uint32_t ra_reg_num = LLDB_INVALID_REGNUM;
RegisterInfo ra_reg_info;
if (m_inst_emulator_ap->GetRegisterInfo (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, ra_reg_info))
ra_reg_num = ra_reg_info.kinds[unwind_plan.GetRegisterKind()];
else
ra_reg_num = LLDB_INVALID_REGNUM;
for (size_t idx=0; idx<num_instructions; ++idx)
{
m_curr_row_modified = false;
m_curr_insn_restored_a_register = false;
inst = inst_list.GetInstructionAtIndex (idx).get();
if (inst)
{
if (log && log->GetVerbose ())
{
StreamString strm;
inst->Dump(&strm, inst_list.GetMaxOpcocdeByteSize (), show_address, show_bytes, NULL);
log->PutCString (strm.GetData());
}
m_inst_emulator_ap->SetInstruction (inst->GetOpcode(),
inst->GetAddress(),
exe_ctx.GetTargetPtr());
m_inst_emulator_ap->EvaluateInstruction (eEmulateInstructionOptionIgnoreConditions);
// Were there any changes to the CFI while evaluating this instruction?
if (m_curr_row_modified)
{
reinstate_prologue_next_instruction = false;
m_curr_row->SetOffset (inst->GetAddress().GetFileAddress() + inst->GetOpcode().GetByteSize() - base_addr);
// Append the new row
unwind_plan.AppendRow (m_curr_row);
// Allocate a new Row for m_curr_row, copy the current state into it
UnwindPlan::Row *newrow = new UnwindPlan::Row;
*newrow = *m_curr_row.get();
m_curr_row.reset(newrow);
// If m_curr_insn_restored_a_register == true, we're looking at an epilogue instruction.
// Set instructions_since_last_prologue_insn to a very high number so we don't append
// any of these epilogue instructions to our prologue_complete row.
if (m_curr_insn_restored_a_register == false && instructions_since_last_prologue_insn < 8)
instructions_since_last_prologue_insn = 0;
else
instructions_since_last_prologue_insn = 99;
UnwindPlan::Row::RegisterLocation pc_regloc;
UnwindPlan::Row::RegisterLocation ra_regloc;
// While parsing the instructions of this function, if we've ever
// seen the return address register (aka lr on arm) in a non-IsSame() state,
// it has been saved on the stack. If it's ever back to IsSame(), we've
// executed an epilogue.
if (ra_reg_num != LLDB_INVALID_REGNUM
&& m_curr_row->GetRegisterInfo (ra_reg_num, ra_regloc)
&& !ra_regloc.IsSame())
{
return_address_register_has_been_saved = true;
}
// If the caller's pc is "same", we've just executed an epilogue and we return to the caller
// after this instruction completes executing.
// If there are any instructions past this, there must have been flow control over this
// epilogue so we'll reinstate the original prologue setup instructions.
if (prologue_completed_row.get()
&& pc_reg_num != LLDB_INVALID_REGNUM
&& m_curr_row->GetRegisterInfo (pc_reg_num, pc_regloc)
&& pc_regloc.IsSame())
{
if (log && log->GetVerbose())
log->Printf("UnwindAssemblyInstEmulation::GetNonCallSiteUnwindPlanFromAssembly -- pc is <same>, restore prologue instructions.");
reinstate_prologue_next_instruction = true;
}
else if (prologue_completed_row.get()
&& return_address_register_has_been_saved
&& ra_reg_num != LLDB_INVALID_REGNUM
&& m_curr_row->GetRegisterInfo (ra_reg_num, ra_regloc)
&& ra_regloc.IsSame())
{
if (log && log->GetVerbose())
log->Printf("UnwindAssemblyInstEmulation::GetNonCallSiteUnwindPlanFromAssembly -- lr is <same>, restore prologue instruction if the next instruction is a branch immediate.");
last_instruction_restored_return_addr_reg = true;
}
}
else
{
// If the previous instruction was a return-to-caller (epilogue), and we're still executing
// instructions in this function, there must be a code path that jumps over that epilogue.
// Also detect the case where we epilogue & branch imm to another function (tail-call opt)
// instead of a normal pop lr-into-pc exit.
// Reinstate the frame setup from the prologue.
if (reinstate_prologue_next_instruction
|| (m_curr_insn_is_branch_immediate && last_instruction_restored_return_addr_reg))
{
if (log && log->GetVerbose())
log->Printf("UnwindAssemblyInstEmulation::GetNonCallSiteUnwindPlanFromAssembly -- Reinstating prologue instruction set");
UnwindPlan::Row *newrow = new UnwindPlan::Row;
*newrow = *prologue_completed_row.get();
m_curr_row.reset(newrow);
m_curr_row->SetOffset (inst->GetAddress().GetFileAddress() + inst->GetOpcode().GetByteSize() - base_addr);
unwind_plan.AppendRow(m_curr_row);
newrow = new UnwindPlan::Row;
*newrow = *m_curr_row.get();
m_curr_row.reset(newrow);
reinstate_prologue_next_instruction = false;
last_instruction_restored_return_addr_reg = false;
m_curr_insn_is_branch_immediate = false;
}
// clear both of these if either one wasn't set
if (last_instruction_restored_return_addr_reg)
{
last_instruction_restored_return_addr_reg = false;
}
if (m_curr_insn_is_branch_immediate)
{
m_curr_insn_is_branch_immediate = false;
}
// Stop updating the prologue instructions if we've seen 8 non-prologue instructions
// in a row.
if (instructions_since_last_prologue_insn++ < 8)
{
UnwindPlan::Row *newrow = new UnwindPlan::Row;
*newrow = *m_curr_row.get();
prologue_completed_row.reset(newrow);
if (log && log->GetVerbose())
log->Printf("UnwindAssemblyInstEmulation::GetNonCallSiteUnwindPlanFromAssembly -- saving a copy of the current row as the prologue row.");
}
}
}
}
}
// FIXME: The DisassemblerLLVMC has a reference cycle and won't go away if it has any active instructions.
// I'll fix that but for now, just clear the list and it will go away nicely.
disasm_sp->GetInstructionList().Clear();
}
if (log && log->GetVerbose ())
{
StreamString strm;
lldb::addr_t base_addr = range.GetBaseAddress().GetLoadAddress(thread.CalculateTarget().get());
strm.Printf ("Resulting unwind rows for [0x%" PRIx64 " - 0x%" PRIx64 "):", base_addr, base_addr + range.GetByteSize());
unwind_plan.Dump(strm, &thread, base_addr);
log->PutCString (strm.GetData());
}
return unwind_plan.GetRowCount() > 0;
}
return false;
}
