void writeConverter(stream<memCtrlWord> &memWrCmd, stream<ap_uint<memBusWidth> > &memWrData, stream<datamoverCtrlWord> &dmWrCmd, stream<axiWord> &dmWrData, stream<ap_uint<8> > &dmWrStatus) {
#pragma HLS INTERFACE ap_ctrl_none port=return
#pragma HLS DATA_PACK variable=memWrCmd
#pragma HLS DATA_PACK variable=dmWrCmd
#pragma HLS DATA_PACK variable=dmWrData
#pragma HLS RESOURCE variable=memWrCmd core=AXI4Stream
#pragma HLS RESOURCE variable=memWrData core=AXI4Stream
#pragma HLS RESOURCE variable=dmWrCmd core=AXI4Stream
#pragma HLS RESOURCE variable=dmWrData core=AXI4Stream
#pragma HLS RESOURCE variable=dmWrStatus core=AXI4Stream
static ap_uint<4> tagCounter = 0;
static ap_uint<16> noOfBytesToWrite = 0;
static ap_uint<16> byteCount = 0;
static enum wcState{WRC_IDLE = 0, WRC_FWD, WRC_STATUS} writeConverterState;
switch(writeConverterState) {
case WRC_IDLE:
if (!memWrCmd.empty() && !dmWrCmd.full()) {
memCtrlWord writeTemp = memWrCmd.read();
ap_uint<32> convertedAddress = writeTemp.address * 64;
datamoverCtrlWord writeCtrlWord = {(writeTemp.count*(memBusWidth/8)), 1, 0, 1, 0, convertedAddress, tagCounter, 0};
noOfBytesToWrite = writeTemp.count;
dmWrCmd.write(writeCtrlWord);
tagCounter++;
writeConverterState = WRC_FWD;
}
break;
case WRC_FWD:
if (!memWrData.empty() && !dmWrData.full()) {
axiWord writeTemp2 = {0, 0xFFFFFFFFFFFFFFFF, 0};
memWrData.read(writeTemp2.data);
if (byteCount == noOfBytesToWrite - 1) {
writeTemp2.last = 1;
writeConverterState = WRC_STATUS;
byteCount = 0;
}
else
byteCount++;
dmWrData.write(writeTemp2);
}
break;
case WRC_STATUS:
if (!dmWrStatus.empty()) {
ap_uint<8> tempVariable = dmWrStatus.read();
writeConverterState = WRC_IDLE;
}
break;
}
}
void simulateTxBuffer(stream<mmCmd>& command,
stream<axiWord>& dataOut)
{
static mmCmd cmd;
static ap_uint<1> fsmState = 0;
static ap_uint<16> wordCount = 0;
axiWord memWord;
switch (fsmState)
{
case 0:
if (!command.empty())
{
command.read(cmd);
fsmState = 1;
}
break;
case 1:
memWord.data = 0x3031323334353637;
memWord.keep = 0xff;
memWord.last = 0x0;
wordCount += 8;
if (wordCount >= cmd.bbt)
{
memWord.last = 0x1;
fsmState = 0;
wordCount = 0;
}
dataOut.write(memWord);
break;
}
}
void readConverter(stream<memCtrlWord> &memRdCmd, stream<ap_uint<memBusWidth> > &memRdData, stream<datamoverCtrlWord> &dmRdCmd,
stream<axiWord> &dmRdData, stream<ap_uint<8> > &dmRdStatus) {
#pragma HLS INTERFACE ap_ctrl_none port=return
#pragma HLS pipeline II=1 enable_flush
#pragma HLS DATA_PACK variable=memRdCmd
#pragma HLS DATA_PACK variable=dmRdCmd
#pragma HLS DATA_PACK variable=dmRdData
#pragma HLS RESOURCE variable=dmRdStatus core=AXI4Stream
#pragma HLS RESOURCE variable=memRdData core=AXI4Stream
#pragma HLS RESOURCE variable=dmRdCmd core=AXI4Stream
#pragma HLS RESOURCE variable=dmRdData core=AXI4Stream
#pragma HLS RESOURCE variable=memRdCmd core=AXI4Stream
static ap_uint<4> tagCounter = 0;
//static enum rcState{RDC_IDLE = 0, RDC_FWD, RDC_STATUS} readConverterState;
//switch(readConverterState) {
//case RDC_IDLE:
if (!memRdCmd.empty() && !dmRdCmd.full()) {
memCtrlWord readTemp = memRdCmd.read();
ap_uint<32> convertedAddress = readTemp.address * 64;
datamoverCtrlWord readCtrlWord = {(readTemp.count * (memBusWidth/8)), 1, 0, 1, 0, convertedAddress, tagCounter, 0};
//ap_uint<16> readCtrlWord = readTemp.address.range(15, 0);
dmRdCmd.write(readCtrlWord);
tagCounter++;
//readConverterState = RDC_FWD;
}
//break;
//case RDC_FWD:
if (!dmRdData.empty() && !memRdData.full()) {
axiWord readTemp = dmRdData.read();
memRdData.write(readTemp.data);
//if (readTemp.last)
//readConverterState = RDC_STATUS;
}
//break;
//case RDC_STATUS:
if (!dmRdStatus.empty()) {
ap_uint<8> tempVariable = dmRdStatus.read();
//readConverterState = RDC_IDLE;
}
//break;
}
void simulateRevSLUP(stream<ap_uint<16> >& txEng2sLookup_rev_req,
stream<fourTuple>& sLookup2txEng_rev_rsp)
{
fourTuple tuple;
tuple.dstIp = 0x0101010a;
tuple.dstPort = 0x5001;
tuple.srcIp = 0x01010101;
tuple.srcPort = 0xaffff;
if (!txEng2sLookup_rev_req.empty())
{
txEng2sLookup_rev_req.read();
sLookup2txEng_rev_rsp.write(tuple);
}
}
void simulateSARtables( stream<rxSarEntry>& rxSar2txEng_upd_rsp,
stream<txSarEntry>& txSar2txEng_upd_rsp,
stream<ap_uint<16> >& txEng2rxSar_upd_req,
stream<txTxSarQuery>& txEng2txSar_upd_req)
{
ap_uint<16> addr;
txTxSarQuery in_txaccess;
if (!txEng2rxSar_upd_req.empty())
{
txEng2rxSar_upd_req.read(addr);
rxSar2txEng_upd_rsp.write((rxSarEntry) {0x0023, 0xadbd});
}
if (!txEng2txSar_upd_req.empty())
{
txEng2txSar_upd_req.read(in_txaccess);
if (in_txaccess.write == 0)
{
txSar2txEng_upd_rsp.write(((txSarEntry) {3, 5, 0xffff, 5, 1}));
}
//omit write
}
}
int main()
{
static stream<ap_uint<16> > clearTimerFifo;
static stream<ap_uint<16> > setTimerFifo;
static stream<event> eventFifo;
event ev;
int count = 0;
//for (int i=0; i < 10; i++)
//{
setTimerFifo.write(7);
//}
while (count < 50000)
{
/*if (count < 100)
{
setTimerFifo.write(count);
std::cout << "set Timer for: " << count << std::endl;
}*/
if (count == 9 || count == 12)
{
//for (int i=0; i < 10; i++)
//{
setTimerFifo.write(7); //try 33
//}
}
if (count == 21)
{
clearTimerFifo.write(22);
setTimerFifo.write(22);
}
probe_timer(clearTimerFifo, setTimerFifo, eventFifo);
if (!eventFifo.empty())
{
eventFifo.read(ev);
std::cout << "ev happened, ID: " << ev.sessionID;// << std::endl;
std::cout << "\t\tcount: " << count << std::endl;
}
count++;
}
return 0;
}